Tool/software:
Project Specs:
Vo: 24VDC
Vin: 550V
P=500W
I am using UCC28951 (PSFB topology) IC for DC-DC isolated power supply project. I have a full bridge synchronous rectifier on the low voltage (secondary) side instead of a half bridge synchronous rectifier.
On the secondary side, PWM signals for E and F (SR FETS) coming from the UCC28951 ic are fed to diagonal switches of the bridge through a half-bridge gate driver ic (2EDL8124G3CXTMA1). Recently, I looked at the forum and found that PWM signals for E and F both could be high simultaneously during the free-wheeling duration.
https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1400335/ucc28950-q1-centre-tapped-or-full-bridge-synchronous-rectifier?tisearch=e2e-sitesearch&keymatch=UCC28951%252525252525252520full-bridge#
In our project, under the same scenario the gate drive ic would not pass PWM signals to the switches when both the signals (E and F) are high simultaneously and hence it will avoid shoot through. At the same time the anti-parallel diodes would be conducted during the free wheel time.
Do you see any issue in our design?
I have been following the TI design https://www.ti.com/tool/PMP7246. It uses UCC 28950 (PSFB) and in its schematic it is clear that E and F PWMs go to the secondary (low) side of the bridge. I have replicated the design. What is the issue here and why are you not recommending to use E and F Pwm signals to drive the secondary bridge?
Thank you.