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Original question:

TPS3613-01: TPS3616-01 RESET outputs behavior when VDD is 0V

TPS3613-01: Positive RESET output behaving as open collector instead of push-pull when on battery power

Nick Nick
Prodigy 80 points
Part Number: TPS3613-01

Tool/software:

The table on page 2 of the datasheet implies the positive RESET output (pin 7) should be the opposite of the /RESET output all the time. The rest of datasheet implies these pins are always push-pull outputs.

However, in the case where SENSE is less than VIT, VDD is zero, and VBAT is 3V, the RESET output appears to be floating, not driven. As far as I can tell, though, the /RESET output is properly driven to GND.

Is this an error in the datasheet, or an error in the component? I have tried three separate parts for good measure, and all behave the same. (I would really like it to be a manufacturing error because I need that pin to be push-pull even when VDD is zero, though I'm not getting my hopes up)

Thank you.

  • 0
    Prodigy 80 points

    I would also like to note the timing diagram shows the /RESET behavior is specifically deterministic when VBAT is high but VDD is low. There is no diagram for positive RESET, so I had implied it would behave the opposite of /RESET. It appears that's an incorrect assumption?

  • 0 in reply to Nick Nick
    TI__Mastermind 18880 points

    Hi Nick,

    I will have to check with our design for this information. My assumption would be that the pFET of the push-pull of the RESET output is tied to the VDD line and not the VOUT line.

    One way to check this is to connect a 2V to the VDD, or any voltage that is below the Vbat and Vit but greater than VDDmin, and check if RESET if 2V

    Jesse 

  • 0 in reply to Jesse Villanueva
    Prodigy 80 points

    I just checked, that is indeed what's happening. The RESET output will follow the voltage on VDD.

    I don't suppose there's any chance there will be a version of this chip where RESET follows VOUT instead? At the very least, I highly encourage a datasheet fix. This has thrown a wrench in my plans unfortunately.

  • 0 in reply to Nick Nick
    TI__Mastermind 18880 points

    Hi Nick,

    Unfortunately we currently do not have an updated device for the tps3613 in our roadmap. I will look into having a next revision of the datasheet.

    Jesse

  • 0 in reply to Jesse Villanueva
    Prodigy 80 points

    If I wasn't using the /CE gating function, would it be a valid substitute to tie /CEIN to +RESET and use /CEOUT as a pseudo-opposite to /RESET? I only need the +RESET output to assert high (and remain high) when VDD is less than VBAT. When VDD>VBAT, +RESET must be low. It's tied to an N-ch FET to make an open-drain output.

  • 0 in reply to Nick Nick
    TI__Mastermind 18880 points

    Hi Nick,

    If you tie /CEIN to GND, it should work, but there will be a 15us transition delay from LOW to HIGH on the /CEOUT.

    Jesse