Other Parts Discussed in Thread: LM51581, LM5158
Tool/software:
I am designing a boost converter with the LM51518-Q1 and have worked through the design process using Webench and the Excel tool, and simulation to define values and an overall solution. I am boosting 12V to 50V, with low current <100mA. I have also attempted to do some simulation with PSpice for TI. I have some questions:
I am concerned about the switch node voltage ring exceeding the 85V limit for the part. Despite very good layout techniques, I would still expect typical ringing to exceed this value albeit for a short period of time. Based on this I have spec'd 200V caps (ceramic MLCCs), so the case size and hence my design solution is generally large - not sure if I'd expect any audible sources here. The solution size also limits the ability to reduce loop areas. But, I have seen several designs on the E2E forums with this part from users that have been 'certified' by TI that are similar in the boost topology creating about 48-50V. None of these have snubbers.
Is there a reason for this?
What sort of reliability degradation may result?
I don't see waveforms that would expose the full switching node signal, but I'd still expect artifacts to exist.
For my design, I have provisioned a snubber for my design to limit EMI and improve reliability. I will be experimenting with values optimize a solution. However, it still requires that the first time the circuit operates, is without any damping circuit that would provide protection to the chip, and also limit EMI. This seems a problematic scenario. My output diode is also rated to 200V, which will also provide a higher capacitance and parasitic impacts.
Can you comment here?
So, I have been attempting to do some simulation using the 2024 version of PSpice for TI (as the transient model is locked by TI), and I have not been able to glean much information regarding the switching node, even though I have added some parasitics to the simulation circuit for rough estimates to the board to try to expose some of the expected behavior. The simulation takes very long to run to gather even 25ms of operation. Reducing some of the convergence values causes very inconsistent results. For example, sequential runs may sometimes show that the device actually runs properly providing regulation and convergence, many times not, and often erroring out before it begins. So, the design cycles have been very frustratingly long to say the least.
I have prototyped the circuit and will have this breadboard in hand very shortly, so I'm preparing as much as possible to understand what I might encounter.
Do you have any suggestions? I cannot post my circuit here, but can provide offline.
Thank you.
