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Tool/software:
hi team:
We are using TPS62873QWRXSRQ1 for DDR power supply with 5V input voltage, while I reboot the load (DDR PHY), the output voltage of this buck experiences slight voltage drop. And I checked the datasheet, seems this chip has the load regulation that output voltage increases with the increase of output current. Ps. remote feedback is implement already.
My question is, if the load current gets lower, this buck will decrease the duty cycle and eventually decrease output voltage, am I correct? Or is this just a matter of accuracy at light and heavy load.
Thanks
Hello Lelian,
Thanks for reaching out to us.
In an ideal case, the duty cycle should not varies with the load current change, instead it's only the inductor current which adopts to it. However, because on-state resistance (Rdson) of the high-side and low-side FETs increases with higher drain current (drain-source current of the FET), the voltage drop across the FETs rises as the output load increases. And to compensate for the higher voltage across the power FET, the duty cycle need to increase to maintain the output voltage regulation. To summarize, the duty cycle typically increases as the load current rises.
On the other hand, the decrease in Vout at lower load is related to the behavior of the feedback circuit and not with the decrease in duty cycle.
I hope I was able to address your queries.
Best regards,
Excel
hi Excel:
Thanks for the explanation, could you please explain more about how feedback circuit is related to the decrease in Vout at lower load? I would like to understand more about this behavior. We implement remote sense already, is it related to the slight voltage drop on feedback circuit because of trace resistance?
Hi Lelian,
The slight increase in Vout at higher the load current higher could be partly attributed to the VFB variation with respect to temperature. In any case, the 1% Vout tolerance covers across PVT (process, Vin, temperature) variations.
The remote sense compensate for the voltage (IR) drop on the system load due to PCB trace resistance which is relative to output current. And the slight decrease on output voltage at light load condition is not related to remote sense function.
Do you have concern on the Vout regulation in your application? Does it go over the limits?
Best regards,
Excel
hi Excel
It does not go over the limits, just wondering how this behaviour comes. I am not sure if this decrease will increase at other test cases if I do not know the root cause. If it's unavoidable due to temperature or other environmental aspects, then I can just leave it there.
So from your point of view, can I leave the slight decrease on output voltage at light load as long as the output voltage is within limits?
Thanks
Hi Lelian,
Typically, SoC CPU/Core rails or any system load have Vout tolerance (ex. 5%) that it can accommodate. You just need to allocate 1% tolerance on DC accuracy to cover DC, Line and load regulation for TPS62873-Q1. And the remaining Vout tolerance will be for ripple voltage, transient load variation, voltage monitoring (if any), etc. See a sample output voltage deviation budget below for reference.
What is the voltage regulation specs of the VDD_DDR rail?
Best regards,
Excel
hi Excel:
The voltage tolerance is indeed 5%, thanks for your explanation, I think your answer resolved my issue