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TPS6594-Q1: PMIC TPS6594133A-Q1 sequence questions

Part Number: TPS6594-Q1


Tool/software:

hello sir,

We use the J784S4 PDN-3A power supply scheme(SOC: TDA4AL), when we test TPS6594133A-Q1 sequence,we found that one power supply has a large deviation from the PDN-3A. 

As shown below, the timing difference between EN_3V3_VIO and VDA_DLL_0V8 should be 4ms .

but the test found that it was actually only 3.66ms, as shown below:

My question is:
1. Why is there this deviation?
2. Does this deviation affect the normal operation of SOC?

  • Hello Baoqing,

    Please allow for some time to dig up documentation explaining this discrepancy.

    Can you first answer some questions for me so I can better assist you?

    1. What document are you pulling that timing chart from?

    2. On the oscilloscope capture, on "EN_3V3_VIO"  is the GPIO signal or the output of the IC it enables?

    BR,

    Nicholas McNamara

  • Hi :

    1.The documents I refer to are attached(J784S4 Single Leo Dual HCPS PDN-3AFGM v0.23b)

    J784S4 Single Leo Dual HCPS PDN-3AFGM v0.23b.pdf

    2. "EN_3V3_VIO"  is the GPIO9 signal of TPS6594133A-Q1.

  • Hello Zhu,

    The document refers to the Rev5 of the TPS6594133A.

    The timing marking in the diagram above includes the time it takes for the OV/UV comparators to monitor the rail after the ENABLE signal for the PMIC turns on the resource(PMIC LDO3, VDA_DLL_0V8). Which is to be at 3500us from the time that the instruction on the PMIC is ran, including signal propagation, ramp up to 90%, this is why you see ~3.6ms from the two signals. Below are some snippets from the datasheet and assembly code for the PMIC showing this.

    Assembly code showing the 2000us + 1000us + 500us (at LDO3) starts enabling at 3500us, with the inclusion of 500us, we get 4000us or 4ms.

    Best Regards,

    Nicholas McNamara