• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 63 subscribers
  • Views 204 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCD7138:Is the block diagram correct with its operation?

Yukio Oyama
Prodigy 90 points
Part Number: UCD7138

Tool/software:

Hi all,

I have been researching the LLC SR driver. I've read the datasheet of UCD7138, and I have a question.

In "8.2 Functional Block Diagram (P.11)", there is an OR gate. It ORs the Q and comparator output, and the output is the DTC.

If Q goes to a Low level, the DTC should also be low. However, "Figure 24. Input-Output timing diagram" does not show the DTC as low when the OUT is low at the falling edge of the OUT.

Is the OR gate accurately expressing the operation of UCD7138?

Best regards,

YUKIOOYAMA

  • +1
    TI__Expert 8710 points

    Hello Yukiooyama,

    The DTC will only go low on a falling edge when BOTH the VD and the IN are low. In the first scenario, OUT is low at the same time as the VD pin. So, the DTC will go low.

    However, in the second scenario, the OUT pin goes low but the VD pin stays high. This means that the OUT pin went low before the optimal time. This is reflected by the spike in voltage, which indicates reverse bias. Only once the VD voltage dips below the Vdtc threshold (-150mV) will the DTC also go low.

    Regards,

    Jonathan Wong

  • 0 in reply to Jonathan Wong
    Prodigy 90 points

    Hello, Jonathan-san,

    Thank you for your support. The explanations you wrote in the timing diagram helped me understand.

    Thank you.

    Best Regards,

    YUKIOOYAMA