TLV1117: Thermal dissipation

Hi Nick,

Thanks for your quick reply.Yes, I totally forgot to add max unit temp to the calculation.  I rather not use switching regulator but do know any linear regulator with lower RθJA. if not do you have any suggestion for switching regulator which does not require a lot of components.

Thanks

Hi Amir,

Have you considered the KTT package for TLV1117? It has about 28% better thermal performance than the DRJ package, although it's quite a bit larger. You will see that the trend when you want to get better thermal performance from RθJA in the low 40s or 30s to get to the 20s (C/W) is that the packages will get large. KTT is among the best for thermal performance. 

I've taken a look through our portfolio and I'm not seeing a better option for your application conditions than TLV1117 in the KTT package. 

Regards,

Nick

Thanks Nick,

I have decided to use DFN package base on my calculation the max current I need is 0.1A which put temp on worst scenario(at 40C) at 78.3C which is under 125C.  But i have questions for the layout of this part

- What does below statement mean, (data sheet page 25), do I need do anything specific. 

- Do you have layout guideline for QFN package. specifically adding more copper on Vout to reduce Junction temp.

Thanks

Hi Amir,

Amir Eshraghi said:

I have decided to use DFN package

Did you mean the DRJ (QFN) package as initially intended? Your math below suggests this package. 

Amir Eshraghi said:

- What does below statement mean, (data sheet page 25), do I need do anything specific. 

This statement is pointing out that this package has an exposed metal pad on the bottom that should be soldered to an exposed pad on the board, so to answer your question, yes you need to do this specifically to meet thermal requirements. 

Amir Eshraghi said:

- Do you layout guideline for QFN package. specifically adding more copper on Vout to reduce Junction temp.

In general the copper connected to each pin will help to pull heat from the device, but the majority contributor by far is the GND copper connected to the thermal pad, so extending the copper beyond the thermal pad will help significantly, and additionally using thermal vias to connect the thermal pad to the internal GND layer (I assume you only have 1 GND layer with a 4-layer board) will help the thermal performance. 

Regards,

Nick

Hi Nick,

The problem is the thermal Pad does not connect to GND in this chip, the thermal pad connects to Vout.

Below is the 4-layer board locations

1.Signal/ GND
2.GND
3. VCC
4.Signal/GND

Thanks

Hi Amir,

I missed that detail (it's only old devices that do this), sorry about that. In that case, yes you were correct, you should try adding as much copper to the VOUT net as possible given your board constraints. What I'm not sure of is how exactly the thermal metrics were simulated for this device because most devices have the thermal pad connected to GND, and the thermal metrics are simulated assuming that the thermal pad is connected to the internal GND layer through vias. I can ask our thermal modeling team to see if they have insights into this.

Regards,

Nick

Hi Nick,

Thanks, let me know if your team have any update. 

Hi Amir,

The thermal modeling engineer said that unless it was specifically specified that the thermal pad isn't connected to the internal layers, it likely was. So, the VOUT net (including the thermal pad) was likely connected to the internal PWR layer. If it is possible on your board, it would help spread out heat if you can use some of the VCC layer as the VOUT net. 

Regards,

Nick