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LM61480: SYNC/MODE pin

Brian Gosselin
Expert 4745 points
Part Number: LM61480

Tool/software:

Hello,

The LM61480 datasheet states that the SYNC/MODE pin (pin 12) cannot be left floating.  However, there's an internal 100k resistor (R_SYNC) to ensure that the SYNC/MODE pin doesn't float.  Therefore, would it be alright if my customer's application had pin 12 high-Z for a period of time?

Also, the SYNC/MODE input voltage (min) low and (max) high spec is a bit confusion.  For ex., the spec is SYNC/MODE input voltage high of 1.7V maximum.  Should this actually be a minimum spec?  I.e., you need an input of at least 1.7V for the device to register a high input?

Best Regards,
Brian

  • 0
    TI__Genius 9460 points

    Hi Brian,

    We recommend not to float this pin.

    Below 0.4V it registers at low, above 1.7V it registers as high. This is for PFM/FPWM selection. 

    Regards,

    Rahil

  • 0 in reply to Rahil Ajani
    TI__Expert 4745 points

    Hi Rahil,

    Thanks for the quick feedback.

    I understand the recommendation to not float pin 12.  My question though is will the LM61480 be okay with the high-Z state on this pin until their FPGA is powered up?  My assumption is yes since the LM61480 as an internal 100k pulldown resistor.

    From my customer, "For the higher power switchers, we're synchronizing their switching clocks with our FPGA.  Between the FPGA and the sync pin, we have the TXU0104DTRR level translator/buffer to keep the clock signals high-z while the FPGA comes up.  The switcher's RT pin has an appropriate pulldown for the switching frequency, so that it can operate until the synch signals are generated."

    Best Regards,
    Brian

  • 0 in reply to Brian Gosselin
    TI__Genius 9460 points

    Hi Brian, 

    I asked the design team and CCed you in the email. Closing this thread.

    Regards,

    Rahil