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LM5143: LM5143 in Single Phase for J784S4

ratheesh chandran
Intellectual 805 points
Part Number: LM5143
Other Parts Discussed in Thread: LMR38015, LM5148

Tool/software:

Hello Experts

We wanted to use LM5143 for the J784S4 as per the suggested PDN. We wanted to use LM5143 in SIngle phase.

As per our profile the power requirement is 85W, which is 5V @ 17A. and the other output is 12V @ 1.2A

Is this configuration feasible?

regards

Ratheesh

  • 0
    TI__Guru* 76022 points

    Hi Ratheesh,

    5V/17A and 12V/1.2A should be fine. What is Vin-max here (as this sets the FET voltage rating and thus the power loss at 17A)?

    You may also want to use a single-channel controller for 17A (e.g. LM5148) and use a converter IC for the 1.2A rail (e.g. LMR38015).

    Regards,

    Tim

  • 0 in reply to Timothy Hegarty
    Intellectual 805 points

    Hi Timothy

    Thanks for your answer. I have a follow up question on this.

    Vin Max is 36V. 

    1. Do you see any EMI concerns with a single phase operating at 17A? What special care needs to taken in layout other than layout recommendations?

    2. Our inductor value is 1.5uH with a 440KHz with operating range of 10V to 36V? Is this ok.

    regards

    Ratheesh

  • 0 in reply to ratheesh chandran
    TI__Guru* 76022 points

    Hi Ratheesh,

    You can check the inductor vlaue using the quickstart file -- target 30-40% ripple current. Take a look at this EVM https://www.ti.com/tool/LM25137F-Q1-EVM5D3, as it's setup for 5v and 3.3V out at 20A each, 440kHz, 1uH inductor.

    In terms of layout, provide adequate heatsinking of the high-side FET drain (VIN). Use an EMI filter as needed (see this EVM and the LM5143 EVM for reference).

    Regards,

    Tim

  • 0 in reply to Timothy Hegarty
    Intellectual 805 points

    Thanks Timothy

    Usually in all the application notes its said to keep the SW node as small as possible. Also the low side MOSFET Drain is connected to the SW node and we give vias throughout the layer to keep the temperature rise in check and connected to the heatsink. So in this case the area of the SW node will be higher.

    How do you being a balance between SW node area and thermal.

    regards

    Ratheesh

  • 0 in reply to ratheesh chandran
    TI__Guru* 76022 points

    Ratheesh,

    It's not a good idea to have vias on the SW node, as it means the high dv/dt node also appears on the other side of the PCB. Better to add vias for the high-side FET drain and allow the inductor to heatsink the low-side FET. See the layout guidelines in the data sheet and refer to the LM5143 EVM layout.

    --

    Tim

  • 0 in reply to Timothy Hegarty
    Intellectual 805 points

    Hello Timothy

    While going through the layout suggestions, there was a remark on having seperate AGND and PGND ground planes. However from the LM5143 perspective the AGND is on South of IC and PGND is on North of IC. How does it help having a seperate AGND and PGND ground planes. The current loop for the PGND is no where near to the AGND pins.

    Thanks

    Ratheesh

  • 0 in reply to ratheesh chandran
    TI__Guru* 76022 points

    Hi Ratheesh,

    We have an island for AGND such that it doesn't conduct high-frequency power currents. This is best layout practice and helps reduce noise and ground bounce in the analog circuits.

    Tim