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BQ78350-R1A: Data flash Wear-Out

Gladson E Y
Prodigy 10 points
Part Number: BQ78350-R1A
Other Parts Discussed in Thread: BQ78350

Tool/software:

Once Dataflash wear out flag got triggered in PF status. We cleared it using 0x0029 Cmd. Then we disabled all algorithms which writes to Dataflash and again started the application. It was working fine for a while with FETs closed. 

Then again Data flash wearout flag got triggered in PF status at random moment in that IC. 

We need to understand at what are the cases,TI Bq8350-R2 FW and Bq8350-R3 FW's internal algorithms write to the dataflash

  • 0
    TI__Guru 55096 points

    This is TI proprietary information. We do not publish all possible flash write cases.

  • 0 in reply to Dominik Hartl11
    Prodigy 10 points

    I understand your point that its TI proprietary information. Then I need clarity on below points

    1) Considering a fresh BQ7830-R1A IC purchased flashed with R2/R3 Ti FW, how much time it will take to raise dataflash wearout flag, only by Ti internal algorithms.

    2) For below two cases, we are using Dataflash write to the dataflash address. As I see, data flash write is not a good option as it wears-out dataflash. Can you help suggest for RAM based command for the IC on such cases

           2.1) We have algorithms that need to enable and disable cell balancing by Host IC Bq78350 based on certain conditions. Can you help suggest for RAM based command for the IC to enable/disable cell balancing in middle.

          2.2) We have algorithms that need to write external average gain. Can you help suggest for RAM based command for the IC for changing external average gain.

    Kindly help in this clarification, it would be very helpful.

  • 0 in reply to Gladson E Y
    TI__Guru 55096 points

    #1: This depends on the application (load, charge). The gauge writes to flash depending on several conditions during discharge and charge (termination). A typical system would write to a single flash page once per cycle so you should get at least 20000 cycles.

    #2: There is no direct command that enables/disables the cell balancing algorithm without writing to flash. There isn't a RAM based command for the Ext Cell Divider Gain either.

  • 0 in reply to Dominik Hartl11
    Prodigy 10 points

    #1) Do you mean power cycle or Chg/Dsg cycle here? And when you say "typical" system, do you mean "no faults and no functional checkpoints" in that cycle? What is the probability of having typical cycle in the system? What is the worst case-probability of flash writes in a cycle by internal algorithms?

    #2) For our application, we need to dynamically enable/ disable cell balancing algorithm. and also change external cell divider gain. Can you please help us in this? Any alternative other than flash write if not a RAM command? Its critical for us.

  • 0 in reply to Gladson E Y
    TI__Guru 55096 points

    #1: Chg/Dsg cycle (full charge detection, discharge down to EDV2). The gauge will update FCC, cycle count, lifetimes. It may update auto-offset.

    #2: I don't see how this can be done without writing to flash. There is no RAM based option to enable/disable the cell balancing algorithm.