Other Parts Discussed in Thread: TPSM843620, TPSM843320,
Tool/software:
Hi, I am using TPSM843A26, TPSM843620 and TPSM843320 to generate the necessary rails for a FPGA system, intend to use PG and EN to achieve the require sequencing, however for these series of power module, the PG and EN pin max voltage is 5.5V, but my system input voltage is 12V, can I use the BP5 (internal LDO) as the pull up voltage as shown in below diagram ?
