TPS54262-EP: Startup and stability issues.

Hi Derek

Thanks for writing to us and posting your query with great details. It will be a big help if you could share PH, Vout and COMP node waveforms. Additionally, share schematic file showing component values. Meanwhile I will work on stability analysis of your circuit based on values you provided.

Although, you have provided pole zero locations of compensator network, it will be good to know the component values. 

Thank you

Regards

Onkar Bhakare  

Hi Derek

Is the issue resolved? If not, could you please share the required information for detailed schematic review.

Thank you

Regards

Onkar Bhakare  

Hi Onkar,

Thank you for your replies. I apologize, I completely missed your first reply.

We have made some progress but are still working on it. I have attached the schematic for what I will call our original circuit at the bottom. We have since acquired two TI eval board for testing. One we are keeping original and the other we are using to swap out parts. 

I'll attach more pics later - for now, here is one example of what we are seeing at the output.

100mA load

300mA load

We did purchase an injection transformer. Below I can share some Bode plots. I am not experienced enough to really know what is good and what is maybe borderline, or if we just recorded garbage, but it looks similar to what we should be seeing to me. I understand the gain and phase margins but one thing I'm looking at is it looks like our zero crossover frequency is too low according to the datasheet.

Eval board

Eval board with our circuit (provided below). All components that were different were changed out/removed except the 47uF input cap on the EVAL board was left and not removed. 

Eval board with these changes to our original circuit:
R40 = 400k (switching freq = 250k)
R38 = 715
R42 = 196k
C25 = .91nF
C27//C30 = .560nF
C29 = .018nF

Our original design on our PCB

Our PCB with changes highlighted above

From what I saw - the "Eval board with these changes to our original circuit" had a very nice output signal across all loads. Very stable 5V, it did not decrease under load and and ~50mV ripple. Once we added those changes to our PCB design, while the output looks better than before, it does not look as good as the eval board. 


I will provide scope captures at the requested pins soon. Please let me know if there is anything else I can provide. I did find TI's power stage designer tool and have been using that to help gain an understanding of what is going on. 

Thank you for your help. Sorry I am a week late. 

I have one more bode plot below. This is with the changes made above but C29 was changed to 10uF. The output looks great on the one PCB we tried - maybe 40mV pk-pk ripple with the exception of a 100mA current draw. Then we see some oscillations and something like 70mV pk-pk. One question I have is we see the output voltage decrease as load increases - more than I would think.5.0V at low current and then down to 4.6V at 1.5A. Is this normal, or is there an issue here still?

Getting other scope captures now.

Please see attached for PH, Vout and COMP measurements with the updates shared and the original design as shown in the schematic.
TI waveforms.pdf

We just realized the bode plot with the C29 change and the PDF with the scope measurements (last 2 posts) were done with a 1000uF cap on the output somewhat downstream of the circuit. We were trying different things yesterday and forgot to take that off. Will update shortly with new results. 

Ok, Bode plot for the following component changes from original schematic

R40 = 400k (switching freq = 250k)

R38 = 715

R42 = 196k

C25 = .91nF

C27//C30 = .560nF

C29 = .010nF

Measurements attached in PDF.

TI waveforms 1 (1).pdf

It turns out the voltage drop was due to losses in the system/cables. At the regulator with a DMM, the voltage stays right at 5V. The component changes made at the top of this reply seem to stabilize things from what we can see. Our plan is to update another board and see if this stays true. I guess at this point, I am looking for feedback of our "proposed" updates.

1. Is there anything you can see that is a no-no or should be changed to ensure we are stable and not get caught with any surprises. This past week has been a learning experience and I'm not 100% confident we know exactly what to look for. 

2. Is there anything we can do to cleanup the ripple at 100mA current draw? Not that it is horrible - I assume the regulator is switching into a different mode at this point. 

Sorry about any confusion with the previous results. 

Hi Derek

Thanks a lot for writing back and sharing such detail info regarding the issue. I really appreciate the effort you took in providing the necessary information and progress you have achieved. I feel there is still some scope for improvement in the selection of compensation network and output capacitor.

1. Capacitor voltage rating is pretty close to operating voltage, selected capacitor will undergo significant derating due DC bias effect. The effective capacitance could be 50-80% lower compared to rated value. I would suggest using capacitor with 10V or higher
2.  Although Phase margin looks good enough at light load but during load transient you might see some degradation in performance. Follow the procedure given in the following data sheet section for the compensator network. Target the phase margin above 60 degree and crossover around 20- 25kHz (Note this target crossover will be at maximum load current in your application)
3. Plot the bode at max load current (2A) 
4. You can also check the load transient behavior by applying appropriate load step.

I hope this helps.

Thank you

Regards

Onkar

Thank you for your response. this does help. We did re-run the bode plot at full current and you were correct as the phase margin decreased significantly. I was going over the equations again today and my biggest question is about ESR for the output cap. Our original circuit has (on paper anyways) very low  ESR according to the Murata website (~2mOhm @250kHz). The resonant frequency of the cap is close to 250kHz which concerns me, but also when I run the calculations in the datasheet, I get a very high ESR frequency (244,347Hz assuming all ESRs make a parallel circuit). If I pick a new cap (low ESR tantalum or electrolytic) with ~30-60mOhms of ESR, I get a much more reasonable (?) ESR frequency. 

My question is are we hurting ourselves by using components with such low ESR? I calculated to be less than .167Ohms but it seems like being too small may cause issues or at a minimum make the design harder. Is this true? 

Hi Derek 

You might see some improvement in margin with equivalent ESR in the range of 15mOhm to 30mOhm. But if you increase it further, it could lead degradations in margins. Nevertheless, low ESR what currently present in the circuit, should not be an issue, if you recalculate the compensation components. Let me know if you face any issue or need some clarification in design procedure. 

I hope this helps.

Thank you

Regards

Onkar

Hi Derek

Let me know if your query is resolved or if you have any further questions?

Thank you

Regards

Onkar