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Original question:

LM73100: Startup fails when heavy load is present

LM73100EVM: Latch-off returning from OVLO condition under load

Chris Benwell
Prodigy 20 points
Part Number: LM73100EVM


Tool/software:

Hi,

Using the (U2) half of the EVM board, I have seen the output not recover when OVLO condition is removed - but only when a load is connected to the output.

1) VIN2 = 5.5V

2) J9 jumper removed and VIN connected to pin2 of J9. So EN/UVLO = VIN.

3) OVLO2 TP17 connected to switched 2.5V.

4) 13.5R resistive load connected to VOUT2

I expected that VOUT would = VIN when TP17 = 0V and VOUT = 0V when TP17 = 2.5V. In practice, after applying VIN, the first time TP17 is switched from 0V -> 2.5V, VOUT = VIN -> 0V. However, VOUT remains at 0V, even though TP17 returns to 0V.

It seems that the mechanism is latch-off because disconnecting and reconnecting the EN/UVLO wire restores VOUT (when TP17 = 0V).

I understand that there are internal latch-off circuits for thermal protection and reverse-current, but why does the circuit work at initial turn-on, and not after OVLO event?

Also, if the VOUT load is removed everything works as expected - VOUT is restores when OVLO condition removed.

I was thinking of using the LM73100 in the priority power MUXing configuration as shown in the datasheet - this is why I am focusing on the OVLO mechanism.

Regards,

  • 0
    TI__Mastermind 39295 points

    Hi Chris,

    OVLO should cause fault latching. 

    As you also mentioned, this is only happening when the load is placed.

    Are you seeing any startup issues? Can you probe all signals to double check if others signal are as expected and can you share waveform with Vin, Vout, current.

    Best Regards,
    Arush

  • 0 in reply to Arush Gupta
    Prodigy 20 points

    Hi Arush,

    I read the table as OVLO does not latch internally? Otherwise how would the Oring prioritization circuit in the datasheet work?

    There are no startup issues. The circuits works on initial turn-on - even with the load present.

    After the fault occurs and OVLO is returned to 0V, I have measured the EN/UVLO, OVLO and PGTH and they are as expected.

    Pressing S2 restores VOUT. I am assuming that because EN/UVLO < Vsd(f) the internally latched fault is cleared which turns on the internal FET's.

  • 0 in reply to Chris Benwell
    TI__Mastermind 39295 points

    Hi Chris,

    Chris Benwell said:
    I read the table as OVLO does not latch internally? Otherwise how would the Oring prioritization circuit in the datasheet work?

    Yes, I made a typo while writing previous answer. I wanted to highlight that OVLO shouldn't cause fault latching. 

    Chris Benwell said:
    I have measured the EN/UVLO, OVLO and PGTH and they are as expected.

    Do you have any waveforms?

    Best Regards,
    Arush