TPS7H5005-SEP: Minimum duty cycle

Hey Jesse,

The LEB of the controller adds to the min on time of the controller, so whatever you set that to can effect it.

Outside of min on time I would suggest looking at the CS_ILIM/COMP pin to make sure you aren't limiting the duty cycle that way.

Thanks,
Daniel

I do have the LEB set fairly high at 200ns. Switching period is 4us (250kHz), so that should still result in the minimum duty cycle being somewhere around 7%. Do the deadtime settings also effect the primary output width, or do those only effect the waveform of the synchronous rectifier output?

Hey Jesse,

The dead time would not effect this value.

What is your slope compensation set to?
Very very low resistor values can artificially set a duty cycle limit.

And please verify you aren't hitting the CS_ILIM limit on the pin.
Checking that COMP isn't going to above 2 Vs will also work.

Thanks,
Daniel

Rsc design value is 68k, I tried larger values yesterday up to 680k and that did seem to slightly improve the situation but did not fix the issue. Also confirming that CS_LIM peaks at 0.293V. COMP is nominally at about 860mV and peaks up to 1.5V immediately following when I see the duty cycle hit 25%.

Hey Jesse,

All the information you provided is very useful.
The COMP peaking is odd, but below ~2 V the op amp shouldn't be saturating.

Is it possible that the feedback resistors are incorrect?
Can you measure the voltage at the FB pin to see if it is around 0.6 V?

Thanks,
Daniel

Let me describe the actual symptoms a little better:

Isolated two switch forward converter, 24V to 34V input 28V output. Regulation is correct from 24V to 32V. As I increase the input voltage slowly above 32V, the regulator starts oscillating at about 1/4 the switching frequency. This really looked like subharmonic oscillation from insufficient slope compensation, but the regulator works correctly at input voltages that result in higher duty cycles of around 35%.

Hey Jesse,

That sounds a bit more like a frequency response issue.
Are you able to provide the schematic?
I would be interested in looking at the estimated frequency response.

Thanks,
Daniel

Unfortunately I can't share the schematic. I have made a little progress this morning. Increasing R_SC yesterday did significant reduce the amplitude of the oscillation, and my issues today were caused by noise on the CS_LIM line. Increasing the filtering on that line has fixed that issue at least. Now I can see the original oscillations, although they are much much smaller. I can't see the ripple on the output anymore but can tell the converter is still oscillating by the gate drive duty cycle (varying from 31% to 24% every five or so cycles). I'm going to take some frequency response measurements now that it's reasonably stable and see what the margins are like.

Hey Jesse,

I point to frequency response because if it is oscillating at 1/4 the switching frequency that would be about 62.5 kHz.
When there are issues with the frequency response it oscillates at the crossover frequency.
A crossover frequency of 62.5 kHz would likely cause instability

Thanks,
Daniel