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LM5156: Detection of FB pin tied to GND for flyback mode

Aidan Walton
Prodigy 80 points
Part Number: LM5156

Tool/software:

Hi,

I am developing with this IC and the datasheet states that the COMP pin MIN clamp is released when the feedback pin is tied to ground. According to the datasheet the FB pin is internally attached to both the error amplifier and the PGOOD comparator. How does the IC detect that the FB pin is grounded. Is there a minimum voltage threshold which is considered to be GND, this seems unlikely as otherwise when a non flyback design had zero output voltage the IC would think it was in flyback mode. I can only assume therefore that the IC must have a quiescent voltage on the FB pin and that by grounding the pin a small current it drawn from the IC which is used to detect the state of the pin.

Could you please clarify exactly how this occurs.

Secondly can you tell me exactly how high a voltage is required on the BIAS pin before the PGOOD FET begins to clamp the PGOOD pin to GND. The datasheet suggests that PGOOD is clamped when !EN | UVLO | FB < FB_UVTH.

What happens with the PGOOD FET when power is first applied and the power rails are ramping up. 

Thanks

Aidan Walton

  • 0
    TI__Genius 15545 points

    Hi Aidan,

    Thanks for reaching out.

    Aidan Walton said:
    that the COMP pin MIN clamp is released when the feedback pin is tied to ground.

    To which part of the datasheet do you refer here? When FB is grounded, the internal OTA will source the maximum current into COMP.

    The IC does not detect the grounding.

    Regarding the PGOOD, this indicator will not work in a operation mode with grounded FB. This is because the the FB voltage can never be higher than the FB UVLO threshold.

    Best regards

    Moritz

  • 0 in reply to Moritz
    Prodigy 80 points

    Thanks Moritz,

    They are small matters, for sure the FB pin will rise above zero volts when configured as a boost converter, but in SEPIC mode this will not be the case until the switching starts. In this case I assume the comp MIN clamp will push the comp pin to 1V? 

    Maybe its just my interpretation but the datasheet says on Page 23 

    "The minimum COMP clamp is disabled when FB is connected to ground in flyback topology."

    This statement infers that somehow the IC is testing this condition. 

    In regard to my question about PGOOD. This is not mode specific but rather how the IC behaves at very low BIAS voltages. We have a system that is powered from multiple sources and the LM5156 is just one point of load element in the system. If I have an MCU monitoring PGOOD; at what low level voltage on the LM5156 BIAS pin is its internal FET able to pull low on the PGOOD pin. I assume it has a min threshold voltage below which it can not be pulled low. We can not assume the pullup on the PGOOD is from the BIAS supply. In fact in this case it is not. I want to ensure the embedded development is aware of false signals from the PGOOD pin if the BIAS pin supply has totally collapsed.

    All the best

    Aidan 

  • 0 in reply to Aidan Walton
    TI__Genius 15545 points

    Hi Aidan,

    Aidan Walton said:
    This statement infers that somehow the IC is testing this condition. 

    There s no "flyback mode" the IC can enter and it is not testing th FB ground condition. When the voltage at the FB pin is under a certain theshold (below Vref), the lower clamp is disabled. This is also the case during the complete softstart time.

    Regarding the PGOOD, we do not specify a Vin value, where the switch is still fully turning on. It should be in the range around 1.5 to 2V. However, the lower the input voltage is, the higher the resistance of the internal switch will be. So it would then depend on the used pullup resistor, as well as the threshold at which you detect a "low".

    Best regards

    Moritz

  • 0 in reply to Moritz
    Prodigy 80 points

    Hi Moritz,

    Okay so yeah I get the idea. Actually it is also important that the diode between PGOOD and BIAS is considered. In fact PGOOD gets clamped a few hundred mV above BIAS by this diode as well as the PGOOD FET action. I was just trying to work through all possible states we find the system in. 

    Thanks for your help.

    Aidan