TPS63030: VOUT dropout when transitioning out of power save mode

Green = 3.6V input, Red = VOUT, Blue = MCU_reset_N.

Green = 3.6V input, Red = VOUT, Blue = MCU_reset_N, Yellow = PS pin (hard to see but the pin is being released by the MCU due to POR, not vice versa - there is no resistor pullup or pulldown on this pin).

Hi Clifton,

I am afraid it is an expected behavior during mode transition from PFM and FPWM.

Since device is configured at PFM mode, Pin PS/SYNC is shorted to GND or connected to GND by a resister, right? If this Pin is shored to GND directly, there should be no mode transition so there should be a resister in your actual design, right? How about just change this resister to zero?

Yes, consumption with light load of FPWM mode should much higher than 50uA.

Regards

Tao

Thank you for the response. Regarding the suggestion to ground the PS pin through a resistor, we actually only use our MCU to control this pin (an attempt to save a tiny bit more power).

But even if we add a resistor pulldown, the regulator will still internally switch from PFM mode to FPWM once an increased current is detected, correct? If that is right, then the resistor won’t change the behavior we see, since the mode will change once there is an increased current draw.

Hi   Clifton,

That is a good question, please give me  more time to do some bench tests to confirm. What is acceptable voltage drop during this mode transition?

Regards

Tao

Thank you for checking. Our MCU can power-on-reset at a voltage as high as 1.65V, so we only have 0.135V of headroom when we have the regulator set to 1.8V.

Hi   Clifton,

Got, will share your bench test results ASAP.

Regards

Tao

Hi  Clifton,

I just had a bench test with our EVM, but seems behavior is different with your got. Screenshot as below.

When mode switch to PWM, no additional glitch observed from my side for this device. could you have a double check from your side.

Regards

Tao

Ok this makes sense I think. It must be that the glitch we see over here is just due to sudden current demand and that the device has not actually left PS mode. Only the power save mode's duty cycle has increased. Looking at your capture, it looks like we would expect no visible low frequency sawtooth behavior on VOUT if it is operating in fixed PWM mode, but we do still see it after the glitch in our capture.

I misinterpreted the datasheet saying "At low-load currents, the converter enters power-save mode to maintain high efficiency over a wide load current range" to mean that there was some kind of automatic transition to fixed PWM mode. It does not appear to be the case. Can you confirm?

I assume in your capture that you are toggling the PS pin, not applying a load. I think a more accurate test for us would be a step load from 0mA to 200mA while the IC is forced in PS mode (pin grounded). Our input voltage is 3.5V, output is 1.8V. Could you make a capture under these conditions to see what load transient looks like in PS mode?

Hi  Clifton, 

Following are some explanation about mode transition.

• When device is set at PS mode, device work at PFM mode when load is light and at PWM mode when there is a heavy load. So, yes, there is a automatic mode transition.
• When device is set at FPWM mode, device always work in PWM mode, no matter load is heavy or not.

Screenshot about load transient behavior as below.

In this screenshot, you can see some kind of overshot in the rising edge of Vout, just ignore it, it is because unquickly enough loop of our EC load. Also, the actual voltage drop in the transiant is very depend on the slew rate of Iout. So, what you observed may very different with myside.

Regards

Tao