Tool/software:
We're looking to parallel multiple low RDS(on) GaN FETs for a high current hard switching application.
The integrated gate driver is quite appealing to us, but curious if it's feasible to parallel these devices given the different source potentials from mismatched gate loop inductance. Power density is very important to us so keeping BOM cost low and high space utilization is crucial.
Is there any documentation or recommendations from Ti's side?
