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LP5018: LP5018 POR Spec

Part Number: LP5018
Other Parts Discussed in Thread: LP5012

Tool/software:

Can you please tell me when the LP5018 is ready after obtaining proper Vcc?

In our product, we have noticed that on some of our boards, we get no activity from the LP5018 during boot-up.  Upon further investigation, if we add a one-second delay (it could possibly be shorter) before "talking" to the device, the LP5018 works every time. That makes me believe that the LP5018 needs some time to be ready.

Looking at the datasheet, I don't see anything specified from proper VCC to device ready.

We are using the enable pin to initialize the device upon power-up. Is there a spec regarding how soon we can use the EN pin after obtaining the proper VCC?

Thank you.

  • Hi Michael,

    Actually, the time you can talk to LP5012 will be very short after power up. It's about ms level, so I think one-second will be enough.

    BR, Jared

  • Thanks for your reply. Unfortunately, it doesn't tell me anything. We have tried waiting 100mS, but the device doesn't power up correctly. Only if we wait one full second can we reliably use the device. It seems rather odd. The POR needs to be characterized.

  • Hi Michael,

    I think the device should be powered up after 100ms. Can you please check that the 100ms is starting from UVLO voltage?

    If you mean the whole system start up, I am wondering that if the startup voltage is too slow to rise or any other reason to cause it.

    BR, Jared

  • Hi, Jared -

    That's the funny thing. We power up and wait for the supplies to become stable. Then, we release the reset to the system. As the kernel is booting, sometime during the boot process, we set the enable high on the LP5018 (wait for 1mS, even though the datasheet says 5mS) and write to the device. Unless we put a delay (in this case, 1 second), it will always fail. Everything else in the system boots correctly. I can try a half-second, quarter-second, etc., and see where it fails. The more intriguing question is, why does it fail? The power supplies are stable (+3.3V and +5V), and everything else boots correctly. I did not mention that the enable is tied to +3.3V, and the chip is powered from +5V. Our +3.3V supply is fed off the +5V supply, so the +5V would come up first, followed by the +3.3V. In any case, we have a long reset to ensure all supplies have come up properly. I have attached the schematic we are using.

  • Hi Michael,

    You said "set the enable high" means pullup external EN pin or send the chip_en command to device?

    Btw, do you have any information or feedback error message for the fail connection?

    BR, Jared

  • Hi Jared -

    I should have been more clear. We have a weak pull-up on the EN pin of the LP5018. The signal (FP_RST#)  is tied to a port on our processor that keeps it low during the boot process. When ready to talk to the LP5018, we set the port high (wait 1mS) and start the I2C communication. We do not use the chip_en command.

    Regards, Mike

  • Hi Michael,

    Thanks for your explanation! I will help to confirm it with our designer and verify it on EVM. I will get back to you ASAP.

    BR, Jared

  • Hi Michael,

    Our design have verified on the circuit and I found a spec on datasheet for the "EN first rising edge until first I2C access", it shows me the maximum is 500us.

    So, I think there should be some mistake. Can you please capture your waveform of VCC, EN, SDA and SCL for your startup process? Thanks!

    BR, Jared

  • Jared - I am working on getting you some waveform captures and a more detailed explanation.

    Mike

  • Hi Mike,

    Looking forward to your waveform!

    BR, Jared

  • Hi Mike,

    I will close this thread first, please free to contact me via email (jared-zhou@ti.com) if you have any update on this topic.

    BR, Jared