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TPS65072 Timing question

Aaron Applegate
Prodigy 100 points
Other Parts Discussed in Thread: TPS65072

In the TPS65072 specification "Figure 33. State Machine" indicates that if (from the POWER OFF state) VBUS is applied, the state machine will transition to the POWER OFF 2 state. Since VBUS = 1, the state machine will then transition to the WAIT FOR POWER ON state. Once in this state, the state machine will wait for a negative edge on the PB_IN_N pin before turning on.

My question is: How long after VBUS is applied does the TPS65072 start looking for the edge on PB_IN_N? I am looking for a minimum time. The board I am working with has an implementation where the application of VBUS and the assertion (low) of PB_IN_N are coincident but the TPS65072 does not turn on. Adding an RC time filter to delay the PB_IN_N assertion causes the TPS65072 to turn on, but I would like to make sure I have designed in the correct time delay.

Thanks,

Aaron

  • 0
    TI__Mastermind 23810 points

    I am looking into this.  I will get back to you soon.

    -Clancy

  • 0 in reply to Clancy Soehren
    TI__Mastermind 23810 points

    I tested this in lab using the TPS650732EVM, with no load, and 5V on the USB input.  The minimum time between when power was applied and the system would detect the falling edge on PB_IN was about 52ms.  On my board, any delay less than that resulted in the system staying in the "Wait for Power ON" state.  Please note that this was tested on one EVM board, and that the external components you choose and any loading conditions could affect this start-up time,  Please let me know if you have any more questions.