LM5034: Active clamp MOSFET getting degraded issue

Prasanna S

Part Number: LM5034

Tool/software:

Hi Team,

I have used the active clamp forward topology with interleaved configuration for 250W output (In interleaved each section can source 125W) boost converter design.

Design requirements are listed below

Input voltage range : 12-36V typical 28V - As design calculation during 12V operation input current will be 13A in single section and 26A for both the section.

Output : 250W (Voltage 50V & Current 5A) - Since it was interleaved design Each section can source 50V @ 2.5A (125W).

Step-up transformer turns ratio: 1:5

SWT frequency: 500KHz

Design considered Efficiency : 91%

Power loss for this design calculated around 15W (Calculated for Primary Switching MOSFET, Clamping MOSFET, Transformer, secondary side rectification MOSFET and switching inductor)

Now issue is the clamping P-CH MOSFET getting degraded and it leads component failure during output load test. Since it was design validation I have currently operating single channel alone one more channel gate signals are isolated method.

I have used 2 MOSFET parts listed below both MOSFET's are getting failed 2 times while performing load test (Load current is 0.5A not even loaded full load 2.5A). We could not assume the MOSFET getting failed due to more voltage or more magnetizing current flow or reverse recovery loss.

1) SQS481ENW-T1_GE3 MOSFET P-CH 150V 4.7A 2.57E 62.5W 305pF SMT PowerPAK 1212-8W RoHs - Initial design consideration part having 150V VDS voltage but 4.7A current.

2) SI7113DN-T1-E3 MOSFET P-Ch 100V 13.2A 134mE 52W SMT PowerPAK 1212-8 RoHs - Based on initial design MOSFET failure suspected more current flow dame a device so 13.2A current rating FET replaced with 100V VDS.

As per design magnetizing current is calculated by the below formula

Dmin x Vin_Max or Dmax X Vin_Min / Fsw X Magnetizing inductance = ((12V X 80%) / (500KHz X 46uH) = 0.417A

Also calculated power loss for the clamping MOSFET are conduction loss, Turn off loss and gate charge loss = 0.64W

My query is apart from this parameters is there any further method is available to calculate the power dissipation....?

What are the possibilities to degraded the clamping FET...?

Is there any other method to find out magnetizing current calculation....?

Regards

Prasanna

8 months ago

0 Hemanth Sreeperumbudur 8 months ago

TI__Intellectual 2480 points

Hi Prasanna,

As you may be aware, important feature on active clamp converter is to achieve ZVS or valley voltage switching. Timing (dead-time) is very important.

Even if the power loss estimation is little off, the devices should not be damaged at room temperature provided with proper thermal design. I suspect, it is not power loss that is driving the FET failure.

The question you are asking is not necessarily related to the LM5034 controller. However, I will provide some insights on this.

Firstly, verify the gate drive signals on MOSFETs are healthy, without much ringing and turn-on and turn-off times are as expected. Tune the gate drive, if required.
Please observe the VDS of primary FET and clamping FET along their respective VGS on the scope to see all the timing is indeed correct and you provide just right dead time to achieve ZVS (or valley) on primary FET and no overstress on clamping FET.
As you now seem to have the actual board itself, testing and observing and analyzing the actual waveforms makes more and quick sense than estimations.
I don't see reverse recovery characteristics on -150V active clamp FET, while the -100V FET has the reverse recovery characteristics, but it is of lower voltage rating. Please verify the voltage stresses on each MOSFET. Chose low reverse recovery (fast diode) MOSFET with sufficient VDS rating, based on your observations.

All the best!

Regards

Hemanth

0 Prasanna S 8 months ago in reply to Hemanth Sreeperumbudur

Prodigy 30 points

Hello Hemanth,

Please find the dead time captured image refer as CH1 (yellow) - PRI-SW-FET-Gate, CH2 (Green) - PRI-SW-FET-Drain, CH3 (Orange) - AC-FET-Gate, CH4 (Purple) - AC-FET-Drain

Overall capture

Image-1 Overall dead time probed image Image-2 Primary SW_FET-Gate Vs AC-FET-Gate

Image-3 Switch node rise dead time probed image Image-4 Switch node with gates rise dead time probed image

As of probing data there is no dead time issue observed and as design calculation calculated dead time is 50ns and observed around 61nS.

Also there is no ringing observed in primary side gate as well as drain node.

Regards

Prasanna S

0 Hemanth Sreeperumbudur 8 months ago in reply to Prasanna S

TI__Intellectual 2480 points

Prasanna,

You need to observe the ZVS or valley switching on Main MOSFET. For that, during turn-on of Main MOSFET, look for VDS and VGS of main MOSFET and VGS of clamp MOSFET. I don't see that waveform.

Measure the voltage stress on clamp MOSFET at different conditions, viz. steady state at low VIN, high VIN and no-load, full-load. Also at startup look for worst case voltage stresses.

I don't see you addressed all the comments.

Only a detailed spec and testing to see whether there is any voltage overstress or reverse recovery issue causing this can be understood.

Regards
Hemanth

0 Prasanna S 7 months ago in reply to Hemanth Sreeperumbudur

Prodigy 30 points

Hemanth,

As of my analysis I have replace the P-CH clamping MOSFET SQS481ENW-T1_GE3 (P-CH 150V 4.7A 2.57E 62.5W 305pF SMT PowerPAK 1212-8W RoHs) with SiSS73DN-T1-GE3 (MOSFET P-CH 150V 16.2A 125mE 65.8W 719pF SMT PowerPAK 1212-8S RoHs ).

Now the power dissipation and MOSFET failure issue resolved with 250W load condition.

Thanks

Prasanna

0 Hemanth Sreeperumbudur 7 months ago in reply to Prasanna S

TI__Intellectual 2480 points

Hi Prasanna,

Thanks for confirming the issue is resolved. SiSS73DN-T1-GE3 has both high voltage rating and decent reverse recovery characteristics.

You may please close the thread.

Regards

Hemanth

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LM5034: Active clamp MOSFET getting degraded issue