TPS55288: Schematic review

Bryce Xun

Hi Stefan,

Thank you for reaching out. What is the output voltage and current? What kind of school project/application is used?

1.Add a 0402 0.1uF cap in Vin pin and put it close to Buck leg loop.

2.Where is MODE pin connected to?

3.Add a 0402 0.1uF cap in Vout pin and put it close to IC.

4.Make sure C15 has 2uF effective capacitance with 5V DC bias.

5.Recommend to change L3 to 4.7uH.

6.Can you provide part number of C16-C18, C14 for loop calculation?

Regards,

Mulin

Output voltage should be variied with i2c but Vout max is 20V at 3A max.

Mode should be a jumper to GND.

So the thing is i dont have the board layout just yet. I just finished with the schematic so i could start with routing as soon as i make sure the schematic is okay.

Its just the TPS55288 as the school project. Nothing else.

Can you provide part number of C16-C18, C14 for loop calculation? Can you accept to change the inductor to 4.7uH?

Hi, yes i changed inductor to 4.7u. Is this going ot work?

https://www.we-online.com/components/products/datasheet/7447707047.pdf

But i dont have any part number yet for the rest of the components because i dont know which to choose

I have also made some changes. Can you check?PowerHub_Schematic.pdf

Hi Stefan,

This inductor is ok . If you have chosen components, feel free to let me check. I think you didn't follow the advice above. Recommend to add the 0.1uF cap in Vin, Vout, VCC.

Regards,

Mulin

Oh sorry. I thought those were for the PCB

No problem. For the component choice, you can refer to EVM BOM in the EVM user guide.

Is the formula for the output voltage Vref / Vfb
For example 1200mV/0.0564 = 21.27V ?

Yes!

Youre the best Mulin! How do you like my solution to the net tie with GND and PGND? Is there a better way? Those are solder jumpers X12

Recommend to connect AGND and PGND with a single point connection, Don't use a jumper because it will cause parasitic parameters. Please refer to below. Connect VCC cap to PGND.

For other layout part, please refer to this guideline.5488.TPS55288 Layout Guideline (Rev B).pdf

Eagle does not offer net ties unfortunately

In this case, you can simply use the same NET name for AGND and PGND. Just separate them in layout.

Could you check up on my final schematic so I could proceed to the layout?PowerHub_Schematic_V1R1.pdf

Hi Stefan,

This schematic looks ok to me. Please go ahead with layout.

Regards,

Mulin

Can you accept my request? Want to send you something in regards to my new post 

Hi Stefan,

I have accepted the request.

Regards,

Mulin

Hi, i messaged you. Please check your messages.

Hi Stefan,

Due to bandwidth limitation, I will reply to you next week. Thanks for your patience.

Regards,

Mulin

Hi Mulin,

Thanks a lot for your patience and your help. Will hear from you next week! Happy Holidays.

Hi Stefan,

Do you want me to reply you by message or just reply here?

Anywhere is fine. 

Hi Stefan,

Thank you for your waiting. I think you didn't follow the layout guideline that I send you before. Please notice:

1.Minimize input loop.

2.Output current sense should be kelvin connection. So as drive circuit.

3.Use separate AGND and PGND.

4.Add enough vias(it is not clear in the gerber file).6646.TPS55288 Layout Guideline (Rev B).pdf

Please refer to this file. I will help check after you modify the layout. Please keep this thread quiet before layout is done. Thanks.

Regards,

Mulin

Is that correct now? Regarding the differential pairs only for the moment

Hi Stefan,

It is better now. Can you send the AD file to me?

Well, heres the thing. Its a school project and we were offered to manufacture the board at JLCPCB. Now the problem is that for more thermal vias which are on the pads itself, we would need capped / filled vias but the price increases to 230$. What would you suggest? Also what would happen to EMI if we were not to use AGND since we made sure to keep track of critical loops to avoid noise interference.

Hi Stefan, you can reduce the via quantity. The most important vias is the vias that besides the Vout and GND pin. Please refer to below. And you can reduce vias that far away from the chip.

AGND is recommended. We have dithering function for EMI performance. You can use FPWM mode for better EMI performance.

Regards,

Mulin

Could you send me the layout file via messages? 

Sure, I will send you by message.

Hi, can you check your messages