LP8556: Test mode

Hi Jeff,

Could you please send me your schematic for double check?

BR

Patrick

Hi Patrick,

Here are some questions about LP8556 VLDO (pin19) measured waveform, please help to check:

1. VLDO boot up maximum voltage is 3.6V, does it have impacts with IC?
2. If VLDO doesn’t drop to zero then boot up, does it have impacts with IC?

Thanks!

Jeff

Hi Jeff,

It is ok for the VLDO voltage.

BR

Patrick

Hi Patrick,

Another question is LDO drop down to around 0.8~0.9V before enable pin drive high, will this voltage impact your internal circuit?

Thanks!

Jeff

Hi Jeff,

I will check this with EVM.

Hi Patrick,

May I know any good news? thanks!

Hi Patrick,

Here is the comment from customer side. Do you know any chance to caused VLDO raise up to 9V?

Since your package is WQFN, ESD to damage IC from pin directly seems difficulty

If ESD comes out, suspect this spike voltage will be absorb by PAC29 (10uF) and we did ESD test in this pin before, no damage after ESD test.

The only way we can reproduce as damaged LDO is apply around 9V into this pin and failure mode is similar.

Not sure if we configure un-correctly, that this IC will enter test mode that could bypass high input voltage into this pin directly?

For the latest failure sample ( FA comes out this Friday), after assemble, in our test process, we will check if all LP8556 can be configure and response , means all LP8556 can be work normally after assemble, but after around 5 month’s daily use, we found this failure.

Hi Jeff,

Does customer mean they add a continuous 9V on the VLDO to damage it? May I also have a look at their layout of the VLDO part?

BR

Patrick

Hi Partick,

Yes, so they suspect there have some test mode in LP8556 may passthough high voltage to LDO and caused damaged. Is it possible?

I will asking for the layout file to you later. thanks!

Jeff

Hi Patrick,

FYI.

Hi Jeff,

OK, I will check if this is related to test mode. And give you feedback then.