Tool/software:
Hi,
In my project the IN+ and IN- pins are fed with complementary pulses but there is no Output coming at OutH/L
the Vgs is clampled to -5V
in my design Vdd is 20v and Vee is -5 V
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Hi Keviv,
Can you please check FLT, RDY pin voltage before applying IN+, IN- inputs and also during applying IN+ and IN- Inputs?
If FLT is low, please check OC pin voltage and share the waveforms.
If RDY is low, Please check VCC, VDD and VEE voltages and share the waveforms.
Thanks
Sasi
Hi Keviv,
Very likely, the OC was triggered to create FLT. Good to know that it is working now.
Hi Keviv,
Not necessarily, it depends up on how the OC is implemented.
If the OC implemented as DESAT,
When the FET is conducting then the OC/DESAT charging current is passed through the conducting power FET. If the FET is not conducting (DESAT/ high voltage across) , then it will not have discharge path so will cause the OC capacitor to charge and cause OC FLT.
Thanks
Sasi