Tool/software:
Dear team,
Would I know the PG-pin behavior when VIN<1.8V?
I understand it is lower than recommended operation range thus it is not guaranteed spec. Table 7-1 mentions when VIN<1.8V, PG-pin is undefined. According to 7.2 Functional block diagram, the FET driver comparator will be shut down and be off. Then pull down FET would be off. Therefore PG would be high impedance and pull-up is properly working, PG-pin would be high. Is my understanding correct?
Best regards,
Yuto Kitamura
