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LM7480-Q1: FET turn-off if input source is disconnected (M74800-Q1 vs. LM74700-Q1)

Harry McNally
Intellectual 440 points
Part Number: LM7480-Q1
Other Parts Discussed in Thread: LM74800-Q1, LM74700-Q1

Tool/software:

Hello

The part within the LM7480-Q1 family is the M74800-Q1.

The requirement for a design is an ideal diode on a charger input to a battery. We only need to protect the battery from reverse current back through the charger input so surge and overvoltage protection are an added feature on the M74800-Q1. The CVCC charger provides some regulation of start currents so inrush isn't an issue from out tests.

The design also senses the charger input voltage at an MCU and the circuit has the resistor divider at the M74800-Q1 EN pin to disable the FETs at undervoltage.

The issue to consider is when the charger input is disconnected during charging; that is, typical removal of the charge plug while active.

Datasheet section 9.3.2.1 Reverse Battery Protection (A, C, DGATE) describes:

In LM74800-Q1 the voltage drop across the MOSFET is continuously monitored between the A and C pins, and
the DGATE to A voltage is adjusted as needed to regulate the forward voltage drop at 10.5 mV (typ). This closed
loop regulation scheme enables graceful turn off of the MOSFET during a reverse current event and ensures
zero DC reverse current flow. This scheme ensures robust performance during slow input voltage ramp down
tests. Along with the linear regulation amplifier scheme, the LM74800-Q1 also integrates a fast reverse voltage
comparator. When the voltage drop across A and C reaches V(AC_REV) threshold then the DGATE goes low
within 0.5-μs (typ). This fast reverse voltage comparator scheme ensures robust performance during fast input
voltage ramp down tests such as input micro-shorts. The external MOSFET is turned ON back when the voltage
across A and C hits V(AC_FWD) threshold within 2.8 μs (typ).

If the input disconnects and floats this won't have reverse current. I can put a high value resistor from charge input to ground but I need to understand the minimum reverse current that will turn the FETs off and allow the charge input to decay to an undervoltage condition. That way the undervoltage will disable the M74800-Q1 charge pump and go to shutdown and the MCU can also sense removal of the charger.

I apologise if the datasheet has this threshold and I missed it.

The related question is if the LM74700-Q1 has a similar regulation as above. If so, what input pull-down resistor minimum reverse current is required ? If I can use the LM74700-Q1 it is smaller, cheaper, and requires less support parts as well as meeting the requirements.

All the best
Harry 

  • 0
    TI__Mastermind 48605 points

    Hi Harry,

    LM74800/700-Q1 operate the FET in regulation mode or conduction mode. During regulation mode the gate voltage depends on the load current. Which means when the load current is low, FET RDS_ON is increased.

    The reverse current that needs to flow to trigger the comparator internally is -10.5mV/RDS OR -20mV/RDS. For slow changing voltages RDS will be increased and trigger the comparator easily ensuring 0A of reverse DC current. 

    Whereas for transients, If the FET is working in full conduction mode the reverse current required will be -10.5mV/RDS_ON(LM74800) OR -20mV/RDS_ON(LM74700)

    LM74700-Q1 can be used as well but will lack the disconnect functionality during UVLO.

    Regards,

    Shiven Dhir

  • 0 in reply to Shiven Dhir
    Intellectual 440 points

    Hi Shiven

    This clarifies the operation of the regulation mode. Thank you. We see another benefit of using the LM74800 so any questions below refer to that part.

    To confirm that I have understood, and using the BUK7Y4R8-60E FET selected as Q1 in the datasheet, and our design charger input pin as INPUT (rather than VBATT)

    - with a 2A current flow, Q1 FET Rds will require 5.25mOhms to have 10.5mV as its target forward voltage

    - the maximum Rds of the FET is 4.8mOhms so LM74800 will be in regulation mode with GATE pin providing FET Vgs to set Rds as 5.25mOhm  

    - if the INPUT is disconnected while 2A current is flowing, then FET forward voltage will reduce and the GATE voltage will reduce to raise FET Rds

    - the GATE voltage will reduce until FET Vgs reaches 0 volts (equivalent to no voltage from the charge pump)

    - this means the FET is now in an off-state and so the maximum current that may flow back towards the INPUT is FET leakage and the ANODE Leakage Current (datasheet Figure 7-7) of 23uA at 0V and 150degC

    Q1: is ANODE Leakage Current correct or should I be using the I(REV) I(A) leakage current during Reverse Polarity, (datasheet Table 7.5) of 112uA ?

    Q2: does this 23uA (or 112uA) mean the device is being powered from the supply (battery) connected to VOUT pin at this point ?   

    - assuming FET leakage is 80uA max. at 65degC then we need to sink a total 80 + 23 = 103uA to pull the charge input terminal towards ground. The design can achieve this pull-down by adding a resistor pot-down from the INPUT to drive the EN/UVLO pin.

    - With a pot that sets the UVLO as 5V (rising), when the INPUT is pulled down below 4.5 volts (falling) then the LM74800 enters shutdown

    Q3: does this mean the reverse leakage current reduces to the I(SHDN) current of 5uA or remain as 23uA ?

    Q4: If a pot-down to the EN/UVLO pin holds the LM74800 in shutdown until INPUT reaches 5V, does this avoid the 7500uA quiescent supply current peak in datasheet Figure 7-1 ?

    In this design, the charger input consumption is not critical but the reverse leakage out of the battery and into the "pull-down" pot matters for our application.

    Q5: Finally, if the FET that is selected for Q1 has a higher Rdson than required to achieve 10.5mV, does the LM74800 operate in conduction mode and transition into regulation mode when forward voltage drops below 10.5mV ? This is an obvious question but I wanted to confirm that the transition doesn't have any surprises.

    All the best
    Harry  

  • 0 in reply to Harry McNally
    TI__Mastermind 48605 points

    Hi Harry,

    I will get back to your questions.

    For Q5, yes, the FET will operate in full conduction mode at lower currents if it has higher RDS_ON.

    If current is reduced further, it will be back to regulation mode.

    Regards,

    Shiven Dhir

  • 0 in reply to Shiven Dhir
    Intellectual 440 points

    Thank you Shiven

    I found a high current pull-down was needed for a voltage only reverse sensing on a competitors ideal diode device so this is why I can ask specific questions about the LM74800 operation.

    Looking forward to your feedback.

    All the best
    Harry

  • 0 in reply to Harry McNally
    Intellectual 440 points

    Hi Shiven

    The TI support bot appears to have set Thinks Resolved while I am waiting for your feedback.

    While waiting I attempted initial layout and the pitch of the WSON12 package pins means I can't design it onto our high current board (an embarrassing oversight).

    So I need to revert to using the original SOT-23-6 LM74700-Q1 with the same questions.

    May I suggest that the feedback you receive from the original question is put into this post ? That way, other designers with a similar (open input shutdown with leakage) requirement will have a comparison between the two parts.

    So, for the LM74700-Q1 then, I need to confirm the backflow leakage out of the device while shutdown and also while enabled but with the FET off (blocking reverse current).

    The values of the leakage currents are required to select the EN/UVLO resistor ladder so that the leakage is sunk by the ladder sufficient to drive the EN/UVLO below the shutdown threshold (from enabled) and also to prevent the leakage from raising the EN/UVLO and incorrectly enabling the LM74700-QI from shutdown.

    I can prototype and measure these currents over a range of temperatures and voltages but it would best to have this considered from TI design data.

    All the best
    Harry 

  • 0 in reply to Harry McNally
    TI__Mastermind 48605 points

    Hi Harry,

    The leakage from cathode to anode is defined in the datasheet and is ~2uA max. These are defined at EN = High.

    Regards,

    Shiven Dhir

  • 0 in reply to Shiven Dhir
    Intellectual 440 points

    Thank you Shiven

    In hindsight I could have used this figure in the LM74800 data and included VSNS current and FET leakage. I have everything I need.

    All the best
    Harry