TPS6593-Q1: Pin Configuration

Hello Tirthal,

Tirthal Patel said:

What should be the pin the pin configuration for the Pin (FB_B1,FB_B2,FB_B3,FB_B4,FB_B5) ,should be connect this pins directly to ground ?

And I am seeing in the design file of the AM62A3-EVM ,why Input is given on the FB_B3 Pin (Net name : LDO_3) which comes from the USB-PD Controller ?

You've probably seen by the PMIC's User's Guide (link here) you saw the connection for FB_B3 and wondered why LDO_3 of the USB-PD Controller as well.

In short the reasoning can better be described by the AM62A processor team for that as they made the EVM, my take is that they've incorporated the USB-PD LDO PS interruption to mean shutdown the PMIC and is only selected as such due to it being an EVM, which would supersede the IO consideration. From a production and PMIC perspective please connect it as shown below (from PMIC's User's Guide)

The connection for FB_Bn is as follows:

FB_B1: Route psuedo differentially with FB_B2 to the point of load, FB_B1 on positive plane or positive lead of capacitor at the SoC (Point of Load, PoL)

FB_B2: Route psuedo differentially with FB_B1 to the point of load, FB_B2 on GND plane or GND lead of capacitor at the SoC PoL

FB_B3: No psuedo routing, place at positive plane or PoL capacitor at the SoL from the TPS22965 IO load switch to account for the IR drop across the plane

FB_B4: Same as above route to the DDR4 positive portion of the net (plane or PoL capacitor) to account for the IR drop

BR,

Nicholas McNamara