UCC21551-Q1: UCC21551 dual gate driver configuration

I am trying to simulate the UCC21551-Q1 in PSpice using a single power supply dual-bias configuration, but I am not getting satisfactory results. The gate charge () for the switch is 79 nC,Boot strap diode vf 0.65 Vdd 21v, but the specific switch is not available in the PSpice for TI library. I suspect I may have made an error in configuring the circuit or selecting an equivalent MOSFET model.

Here are the simulation details

Hi Swathin,

It may be an insufficient bootstrap capacitor value (C3 in your schematic).

It looks like there is not enough instantaneous charge to fully bias the high-side channel.

Could you try increasing this value based on the MOSFET total charge?

• Cboot = Qtot / Vvdda

Regards,

Hiroki

Hi 

Qg (Total) of the SiC fet is 79nC Vdda is 21V Vf of bootstrap diode is 0.65, so effective capacitance would be 3.88nF. Ten times of 3.88 would be 38nF i have even tried up to 10 uf instead, but the result is same. this is the parameters added to the ideal mosfet in simulation . when I replace the top mosfet with a capacitor (gate to source with same Ciss 2124p) this is working normal.

Hi Swathin,

Thanks for following up with these details.

That is interesting that it works with a MOSFET replaced by a capacitor.

Can you share the schematic and waveform of this?

Regards,

Hiroki

Finally i did able to simulate with MOSFET as well, with both +ve and -ve biasing, but its working when i am not applying any voltage across the MOSFETS. these are the output waveforms with and without 250V across MOSFETs (Red-Vout1, Green- Vout2, Blue -VDDA). What is causing the VDDA to fall to zero volt when switching.

Hi Hiroki,

Thanks that resolved my issue, am getting pulses at outputs but there is a slight curving at the rising edge of the pulse, compared to the falling. And  small spikes as well  how to resolve this.

Hi Swathin,

Glad that fixed the issue with the channel A output.

The first approach I would try is to increase the bootstrap capacitor value. It may not be providing enough power during the Miller plateau region of the turn-on which may result in that slight dip.

For the turn-off, try playing around with the turn-off gate resistor value to see if this has an effect on the small voltage spike after the turn-off.

Hopefully this helps.

Regards,

Hiroki

Hi Hiroki, 

we selected the " Negative Bias with Zener Diode on Iso-Bias Power Supply Output " configuration since the bootstrap method requiring higher peak input current from the source. i have some doubts in component selection for this configuration.

How to select the capacitor values for CA1 and CA2? in this configuration

hi Hiroki, thanks for your response.

this is the schematic i made for the application but

1. if you check the output waveform upper side gate out is not going to negative side. if remove the ground connection from mosfet bridge the lower side wont go to negative. 

2. if you check the schematic from datasheet there is one more capacitor parallel to the  supply how to calculate the value for that one.

Hello Swathin,

Hiroki must be away from his office at this time. He should respond to your question within the next business day.

Regards,

Hi Swathin,

Swathin ES said:

1. if you check the output waveform upper side gate out is not going to negative side. if remove the ground connection from mosfet bridge the lower side wont go to negative. 

From the schematic, it looks like the probing point for the low-side output is being referenced to the 0 ground which would pull the signal to 0V.

Swathin ES said:

2. if you check the schematic from datasheet there is one more capacitor parallel to the  supply how to calculate the value for that one.

This capacitor is the bulk decap that will provide instantaneous power to the gate driver. A 50V 10uF MLCC will be sufficient for this capacitor.

Regards,

Hiroki

Thanks Hiroki,

That solved the issues 

Hi Hiroki,

i have one more doubt. As per the Equations provided in the data sheet the total power Required for one side is  0.4472W  but in simulation the minimum i could achieve is 1W. Can you please check this and let me know where i did wrong?. the losses from zener and its limiting resister (2.4k) Iis not considered in equation i guess.

Hi Swathin,

From the values you have provided, the calculations look correct.

Do you mind sharing more details about the simulation schematic? Just want to see all of the possible factors that could be included in the simulation that would not be included in the datasheet equations.

Looking forward to hearing back.

Regards,

Hiroki

power mos p parameters are edited as per real switch bias voltage is coming from ucc25800 based power supply

Hi Swathin,

Thank you for the details.

The power loss calculations in the datasheet will include the total power loss inside the gate driver as well as the switching losses.

Bootstrap and negative bias circuitry will not be included in the datasheet calculations.

Could you try measuring the losses from the negative bias network in your schematic to see if the additional power loss is coming from there?

Regards,

Hiroki

Zener diode have 33mW and Zener series resister have 164mW losses measured.

Hi Swathin,

Thanks for following up!

Adding up the total gate driver power required for the driver supplies with the negative bias Zener circuit as well as any ESR from the capacitor models, the total power loss should be closer to your simulated values.

Hope this helps with the question.

Regards,

Hiroki