UCC28056: Maximum Bandwidth Attainable by a PFC

Hello Luca, 

To clarify, the bandwidth of a PFC voltage-loop is usually set below 20Hz so that the compensation network attenuates the twice-line frequency ripple on the COMP pin, is the major contributor to 3rd-harmoinc distortion. 

There is an old app-note on PFC design that addresses the COMP network design to attenuate for a specific amount of 3rd-harmonic THD. 
I suggest that this app-note can be used to target a higher amount of THD as well.
Please review: 
0116.Optimizing High PFC slup093.pdf

Regards,
Ulrich

Hello Luca, 

What you are asking to do is not normal design procedure nor a usual design goal, so I must admit I have never thought about it.  My guess is that there is no procedure established to increase THD while keeping a stable loop.  That is not to say it isn't possible, but I'll have to conduct some thought experiments. 

Start with a normal PFC where ripple on COMP is minimized to allow nearly constant on-time across the line cycle, yet not so filtered that the loop can't provide a reasonable response time to load and line transient events.  This results in allowing the presence of twice-line ripple voltage on the PFC output capacitor with amplitude considered negligible with respect to the average DC level.  We don't try to regulate that ripple down to zero amplitude. 

This ripple amplitude, however small, is maximum at full load, and is generally considered acceptable.
Your initial posting expressed a desire to attenuate some "... fluctuations in the value of Vbus due to small load variations caused by the speed control of the motor."  This suggests to me that the load variations are a small fraction of the average load and that the amplitude of such fluctuations must be small compared to the maximum twice-line ripple voltage on the bus.

My first thought is: "Why would you be concerned about attenuating these fluctuations when the larger twice-line ripple amplitude will still exist if there are absolutely no load variations from speed control?"  

Setting aside the reason why you would want to do so, my second thought is:  "Assuming the goal is to attenuate the fluctuations without trying to regulate Vbus to be "ruler-flat", what is the trend for the COMP ripple voltage as bandwidth increases? "
This leads to: "What is the minimum frequency of the Vbus fluctuations from speed control?"    How high does the bandwidth have to be to have an attenuating effect on that frequency?  Now I get the picture of your main concern with stability. 

Assuming the new BW is near or even above 100~120Hz, then I think the twice-line ripple on Vbus will dominate and the loop will try to regulate out this ripple.  The motor speed fluctuations will also be attenuated, I expect, but line current harmonics will be greatly increased. 
Instead of constant on-time (previously due to very low band-width), on-time will increase at the zero-crossings to try to reduce Vbus falling below average, and on-time will decrease at the line peaks to try to reduce Vbus rising above average.  

This will lead to high peak currents near the zero-crossings which may saturate the inductor. I think this concern has higher priority than loop stability.  
Now, peak inductor currents at near-zero voltage must be limited to be no higher than the usual max peak amplitude at full load, peak of low-line.
Even if that is accomplished, because of the near-zero-voltage input, the long on-time probably drives the switching frequency into the audible range and that can excite vibrations in the inductor to create audible noise.  

Getting back to loop stability.  Stability is based on system response to small-signal perturbations of steady-state conditions, such that small perturbations dampen out back to steady-state rather than increase uncontrollably out of steady-state operation.  
In the wide-BW case, I think the rectified-line voltage variations might constitute significant large-signal perturbations and I am not sure whether the loop can accommodate them.  

In non-PFC applications, certainly multi-kHz loops can keep PWM converters stable when running from bulk caps with considerable twice-line ripple on them.  But that ripple does not go from peak to zero, and the ripple is lower at high-line where loop gain tends to be higher. 

In a wide-BW PFC, "bulk ripple" extends from peak to zero always, even at high line, where the ripple is highest and the gain is highest. 
The UCC28056 feedforward function should help reduce the high-line gain, but I'm not sure if this is enough to maintain stable control. 
I'm not sure if a response analyzer can successfully inject and detect the small-signal perturbations in the presence of the large-signal variations.  

I suggest to conduct a series of experiments of gradually increasing BW to study how the loop responds. I suggest to use a DC load with small load steps at low repetition rate.  Keep increasing BW until signs of poor phase margin begin to appear.   I am unable to help predict the possible results ahead of time since I haven't had the occasion or need to do so.  Perhaps a web-search may uncover some prior work along this line. 

Regards,
Ulrich