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TPS7A91: How to design LDO for FPGA_PL power(requred 10mVp-p)

kenji shimada
Prodigy 210 points
Part Number: TPS7A91
Other Parts Discussed in Thread: TPSM863257

Tool/software:

I am currently designing a power supply for an FPGA PL power supply (requiring 10mVp-p).

The power supply design is 12V-DC -> DCDC (TPSM863257RDXR: 3.3V) -> LDO (TPS7A91: 1.8V).

How should I design this power supply, and how can I check whether it meets the requirements of the FPGA PL power supply?

  • 0
    TI__Genius 12340 points

    Hello Shimada-san,

            A quick check would be to take the TPSM863257's typical ripple value of 20mVpp (from datasheet table 8-1) at approximately 1MHz (from datasheet figure 6-18) and reduce this voltage by ~55dB (estimated from TPS7A91 datasheet figure 2). This results in an estimated output ripple on the 1.8V supply of approximately 36µVpp. 

    Output ripple from the TPSM863257 will depend on the ESR of your selected output capacitors. A more accurate estimate of the output ripple can be calculated by following this application note: https://www.ti.com/lit/an/slva630a/slva630a.pdf. Ripple attenuation in the LDO can then be estimated from the datasheet curves as above. 

    Another option would be to simulate your power delivery network with PSpice for TI - we have models available for both the TPSM863257 and TPS7A91 on their respective product pages. This option would also allow you to simulate both your FPGA's estimated load conditions and transients and can incorporate the effects of capacitor ESR and ESL. 

    Best Regards,

    Alex Davis