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Original question:

TPS7A57: Question about Bias Pin on the TPS7A5701

TPS7A57: Simulation of startup

TInMan
Prodigy 30 points
Part Number: TPS7A57
Other Parts Discussed in Thread: TPS7A85

Tool/software:

Hello,

I'm upgrading a design that was using the TPS7A85 4A regulator. We will be drawing at least 3.2A per LDO, so to give some additional headroom I was thinking of switching over to the TPS7A57. Maybe not necessary, but wanted to at least simulate this new LDO.

I downloaded the PSpice for TPS7A57 and imported it into LTSpice. I setup a circuit to generate 2.4V from a 3V input. This works fine when just providing the DC voltage and doing a transient analysis.

I wanted to simulate the turn-on behavior of the LDO, so I switched my supplies to a pulse, starting from 0V. This completely kills the output. Am I doing something wrong? I tried configurations using the BIAS input instead of the charge pump, but nothing seemed to fix the behavior. Is this an issue with the model or something I'm doing? The model text says the startup behavior is modelled, so I figured I should be able to see it startup after turning on the ENABLE.

Vout seems to only respond when Vin is ramping up (and is obviously very small). 

Also, the voltage on the reference pin is the 2.4V that I want on the output, and is present when I turn on the enable. 

Please let me know if there is any obvious error, or an issue with the model, or maybe with how it was imported by LTSpice? 

Thanks

  • 0
    TI__Genius 12675 points

    Hello, 

    Thank you for reaching out. 

    Since LTspice is a SPICE simulator owned by a different company, we cannot give any LTSpice support. 

    In regards the model, have you tried running the same type of simulations in PSpice? I will try to run this in PSpice and correlate as well, but I don't see any concern with the circuit you have shared. 

    Best, 

    Edgar Acosta

  • 0 in reply to Edgar Acosta1
    Prodigy 30 points

    I haven't installed any other Spice simulators. Short of doing that, I posted here first. If you get around to running this in PSpice, that would be great!

    Thanks again

  • 0 in reply to TInMan
    Prodigy 30 points

    Ok, I installed PSpice for TI. But this seems to be the only part I can't actually place. The file is in the library, but I'm getting this error message:

    I even replaced the file with the one I downloaded the other day, and that didn't help.
    I can drag the .olb into my project (is a file in Design Resources), and I can open it and see the part drawing... but I can't place it.

  • 0 in reply to TInMan
    TI__Genius 12675 points

    Hi TinMan, 

    I'll take a look at this today. I assume you are using the model that is currently available online, correct? 

    Best, 

    Edgar A.

  • 0 in reply to TInMan
    TI__Genius 12675 points

    No worries, we will take a look and take it from there. 

    Best, 

    E.A.

  • +1 in reply to Edgar Acosta1
    TI__Genius 12675 points

    Hi TinMan, 

    I downloaded the PSpice model from the TPS7A57 product page, and I was able to open it without any issues: 

    I went ahead and recreated your schematic. I did have to tie VBIAS to GND since in PSpice you cannot leave a node floating (dont know if LTspice has the same issue)

    Also, I noticed that your time window is only 400us. Ideally the model should also start ramping Vout when EN rises, but there is a delay (~2.3ms) in the model from when the LDO is EN to when VOUT should start rising.

    This doesnt happen with the real device.

    This delay seems to be coming from the fact the model tried to capture the turn on / ramp rate feature of using different values of the Cnr/ss capacitor

    With a 4.7uF the estimated soft start ramp rate  tss ~ Vout(target) *Cnrss / Iss -> 2.4*(4.7uF)/200us -> tss ~ 56.4ms

    Can you try increasing the time window in LTspice? 

    Best, 

    Edgar A.

  • 0 in reply to Edgar Acosta1
    Prodigy 30 points

    That was it, thanks! I was getting really long simulation times at one point which I didn't understand, so I was keeping the analysis short. This is great though!