TPS65220: TPS65220

Hi Sathish,

Thanks for the prompt response.

Sathish hereby attaching the PMIC Schematic section PMIC SCHEMATIC PAGE FOR TI REVIEW.pdffor TI verification. Request you to verify the PMIC circuitry and its configuration and provide your comments.

Note: The PMIC input supply provided is 5V (V_IN=5V)

This would help us on stabilizing the design.

Thank you.

Hi Sathish,

A gentle reminder on the above request.

Request you to provide your comments ASAP.

THANK YOU.

Hi Amarnath,

Our standard time for schematic review is one week. I will review the schematic and provide my feedback by next Monday. Thank you for your patience.

Sathish

Hi Amarnath,

Thank you for the patience, i reviewed the schematic and here is my feedback,

- I see I2C lines are pulled up to Buck2 output, we recommend to connect it to an external rail or MCU power so that it is not dependent on PMIC output.

- I see LDO1 and LDO4 are not used but since this device has those rails programmed ON, it is good that you have output caps for these.

- I see Buck outputs have 47uF cap but if you planning on using max load, i would recommend to increase the cap value because Bucks are configured in High Bandwidth

Not sure if you have already seen this, but here is the TRM for this device. Please review once and let me know if you have any specific questions.

https://www.ti.com/lit/ug/slvucj3/slvucj3.pdf?ts=1739550456990&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTPS65220

Sathish

Amarnath,

Just to be more clear, 47uF is enough for stability but more capacitance is needed for better load transient response.

If you look at the device D/S specifications, 1A load step is defined with 80uF cap.

Sathish

Hi Sathish,

Thanks for your valuable feedback.

Just 1 point to confirm here he V_IN is +5V (i,e.: VSYS, PVIN_B1, PVIN_B2, PVIN_B3 & PVIN_LDO1 = +5V)

Since we are supplying +5V to the PMIC, we are Powering AM64x processor on a system with +5V input supply This should not be a problem, right?

Thank you.

Hi Amarnath,

US in on public holiday 17th of Feb. They will come back to you next business day. 

Br, Jari

Hi Sathish, 

Thanks for your valuable feedback. 

We see in the TI EVM-SK schematic, Ti has also used 1x47uF & 1x0.1uF. Also, can you please show me where in the device D/S "1A load step is defined with 80uF cap" shown?

The reason behind asking this is, since we are designing the OSM-M standard board we have a space constraint.

Since 47uF is the maximum capacitance value we are able to get on 0603 package. Now if we need to increase the capacitance value, we only have to add the bulk capacitors, so adding more Bulk caps on the Buck outputs is a big challenge from the placement standpoint. 

Since the Maximum Power consumption on Buck-1 Rail is 2A, Buck-2 Rail is 1.22A & Buck-3 Rail is 0.7A.

So, adding 1 more 47uF on Buck-1 rail alone should be fine and keeping the Buck-2&3 output capacitors as it is?

Thank you. 

Hi Sathish, Jari, please help to share your comments on Amar's query.

Hi Amarnath,

Please see the load transient sepc on Page12 of the below data sheet.

https://www.ti.com/lit/ds/symlink/tps65219.pdf?ts=1739463134745&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTPS65219

Buck2,3 Load transient is specified on Page14, with same Cout of 80uF for High Bandwidth config.

DC operation is not a problem with minimum cap but please review the transient spec meets the application requirements.

Sathish

Hi sathish,

Thanks for your feedback.

Now Since 47uF is the maximum capacitance value we are able to get on 0603 package. Now if we need to increase the capacitance value, we only have to add the bulk capacitors, so adding more Bulk caps on the Buck outputs is a big challenge from the placement standpoint. 

Since the Maximum Power consumption on Buck-1 Rail is 2A, Buck-2 Rail is 1.22A & Buck-3 Rail is 0.7A.

So, adding 1 more 47uF on Buck-1 rail alone should be fine and keeping the Buck-2&3 output capacitors as it is?

Hi Amarnath,

If they don't expect any load transients then that should be okay for normal operation but unfortunately all 3 Bucks load transients requires same Cout of 80uF.

Sathish 

Hi Sathish,

In our design we are using TPS6522053 with VSYS=5V. The same 5V has also been fed to the PVIN_LDO1 (Pin No: 6). Now since as per the default NVM configuration the LDO1 is in Bypass mode and so the PVIN_LDO1 has the limit of up to 3.6V only.

Now how to proceed in this case? What happens if I provide 5V to PVIN_LDO1 pin?

As you stated above that "the default configuration of LDO1 is in bypass mode so the sequence of steps should include power up PMIC with PVIN_LDO1 at 3.3V" how to handle this sequence now?

Just Pulling down the VSEL_SD/VSEL_DDR pin to ground will solve this issue?

Thank you.

Hi Sathish,

Also, in our design if you see we are not using the LDO1 output. In that case what should be the termination followed for PVIN_LDO1 pin? Providing +5V to PVIN_LDO1 will not damage the pin/internal circuitry or malfunction the chip?

Thank you

Hi Sathish,

Regarding the Bulk Capacitance on the Buck-2 & 3 outputs, since our Buck-2 output is 1.8V & Buck-3 output is 1.1V and as the datasheets says that for 1.8V output, forced PWM condition for load transient from 1mA to 1A the Cout=40uF. 

So, in this case our Buvk-2 & Buck-3 output capacitance of 47uF each should be fine right?

Thank you.

Hi Amarnath,

Sathish is out of office today but expected to return Monday. 

Regards,

Katie

Hi Sathish,

We see in SK schematic that the input capacitor for PMIC-Buck-1,2 & 3: (4,7µF 0402 10V) GRM155R61A475MEAAD AC 1Vrms capacitor is used.

Whose derating is: change rate -44% for 3,3V and Capacitance 2,5µF at 25°C as per the Murata SimSurfing tool, which doesn't meet the minimum input capacitance required. 

Can we please know the reason behind this?

Thank you.

Hi Amarnath,

Agreed, if the PCB size allows then larger capacitance is recommended.

Sathish

- I see I2C lines are pulled up to Buck2 output, we recommend to connect it to an external rail or MCU power so that it is not dependent on PMIC output.
Reply: Since the I2C lines are connected to the AM6442 I2C lines which are 1.8V level and powered by BUCK2 output, we wanted to Pull up this I2C lines to the same.

Now the question will this have any issue due to the power sequencing since the PMIC_BUCK2 output comes delayed?  

Hi Sathish, Request you to provide your comments on the below query


Regarding the Bulk Capacitance on the Buck-2 & 3 outputs, since our Buck-2 output is 1.8V & Buck-3 output is 1.1V and as the datasheets says that for 1.8V output, forced PWM condition for load transient from 1mA to 1A the Cout=40uF. 

So, in this case our Buck-2 & Buck-3 output capacitance of 47uF each should be fine right?

Thank you.

Hi Sathish,

Request you to provide your comments on the below query as well.

In our design we are using TPS6522053 with VSYS=5V. The same 5V has also been fed to the PVIN_LDO1 (Pin No: 6). Now since as per the default NVM configuration the LDO1 is in Bypass mode and so the PVIN_LDO1 has the limit of up to 3.6V only.

Now how to proceed in this case? What happens if I provide 5V to PVIN_LDO1 pin?

As you stated above that "the default configuration of LDO1 is in bypass mode so the sequence of steps should include power up PMIC with PVIN_LDO1 at 3.3V" how to handle this sequence now?

Just Pulling down the VSEL_SD/VSEL_DDR pin to ground will solve this issue?

Hi Sathish,

Request you to provide your comments on all the above open points ASAP.

Thank you.

Hi Sathish,

Since the CESR for LDO1,2,3 &4 output is mentioned as 20mΩ max as shown below, can you please confirm if that CESR is for Cout alone or the Cout_total?

  
Thank you.

Hi Sathish VallamkondaBrenda Diaz

Request you to please provide your thoughts on the above open points asap.

Hi Amarnath,

AMARNATH G said:

Hi Sathish,

Since the CESR for LDO1,2,3 &4 output is mentioned as 20mΩ max as shown below, can you please confirm if that CESR is for Cout alone or the Cout_total?

It will be Cout alone.

Amarnath,

As Sarah mentioned in other thread, pulling down VSEL_SD pin to GND will not make LDO switch from Bypass mode to LDO mode.

Sathish

AMARNATH G said:

Regarding the Bulk Capacitance on the Buck-2 & 3 outputs, since our Buck-2 output is 1.8V & Buck-3 output is 1.1V and as the datasheets says that for 1.8V output, forced PWM condition for load transient from 1mA to 1A the Cout=40uF. 

So, in this case our Buck-2 & Buck-3 output capacitance of 47uF each should be fine right?

As mentioned before all 3 Bucks have same capacitance requirement in terms of load transient. For DC operation it is okay, but to meet transient spec a min. of 80uF capacitance is required. A less capacitance will results in large voltage transient. Now, looking at the DC bias de rating of the caps, value of the capacitor is even higher.

Sathish

AMARNATH G said:

- I see I2C lines are pulled up to Buck2 output, we recommend to connect it to an external rail or MCU power so that it is not dependent on PMIC output.
Reply: Since the I2C lines are connected to the AM6442 I2C lines which are 1.8V level and powered by BUCK2 output, we wanted to Pull up this I2C lines to the same.

Now the question will this have any issue due to the power sequencing since the PMIC_BUCK2 output comes delayed?  

That should be okay. 

AMARNATH G said:

Also, in our design if you see we are not using the LDO1 output. In that case what should be the termination followed for PVIN_LDO1 pin? Providing +5V to PVIN_LDO1 will not damage the pin/internal circuitry or malfunction the chip?

Amarnath,

If you have a 3.3V, i would recommend it to connect to that volage level. Or if you have 1.8V, then you can pull down VSEL_SD to GND and connect PVIN_LDO1 to 1.8V. Hope that makes sense.

Sathish

Hi Sathish,

As you fully go through the thread (+) TPS65220: TPS6522053 with VSYS=5V/PVIN_LDO1=5V/VSEL_SD=pulldown - Power management forum - Power management - TI E2E support forums in which the other threads are also linked for better understanding,

So, as a conclusion my understanding from the thread (+) TPS65220: TPS6522053 with VSYS=5V/PVIN_LDO1=5V/VSEL_SD=pulldown - Power management forum - Power management - TI E2E support forums is that PVIN_LDO1 can be connected to +5V when VSEL_SD pin is Pulled Down.

When VSEL_SD is Low, LDO1=1.8V (Behaves as a Fixed 1.8V LDO). Now when LDO1 is configured as LDO mode then the PVIN_LDO1 pin can have a input voltage between 1.5V to 5.5V.

Kindly confirm if my understanding is correct from the below threads

1) (+) TPS65220: TPS6522053 with VSYS=5V/PVIN_LDO1=5V/VSEL_SD=pulldown - Power management forum - Power management - TI E2E support forums

2) (+) TPS65220: PMIC features understanding - Power management forum - Power management - TI E2E support forums

3) (+) TPS65220: TPS6522053RHBR - Power management forum - Power management - TI E2E support forums

Thank you.

Hi Sathish,

I am sorry for repeating the same question again, when we look at the datasheet as shown below

To meet transient response for Vout = 1.8V, the Cout recommended is 40uF as highlighted above. Thats where I want to confirm since in our design BUCk-2 output is 1.8V & Buck-3 output is 1.1V should 47uF as the output capacitor enough?

Thank you,

Hi Sathish,

So, Pulling Up the I2C lines to Buck2 output shall not have any issues regarding the I2C communication with AM6442 later, correct?

Also, from the power sequencing point of view also we shall not have any issues later. 

Is my understanding correct?

Thank you. 

Hi Sathish,

For PMIC LDO2 output capacitor, we have used 10uF as output capacitor, but the datasheet recommends having 4uF max as a output capacitor as shown below 

Can you please provide clarification for having 10uF as output capacitor?

Does the above snapshot make sense?

Thank you.

Amarnath,

Thanks for those references from Brenda. I also confirmed with our System Engineer that it will automatically switch to LDO mode at 1.8V, so you can leave PVIN_LDO1 at 5V. Sorry for the confusion.

AMARNATH G said:

For PMIC LDO2 output capacitor, we have used 10uF as output capacitor, but the datasheet recommends having 4uF max as a output capacitor as shown below

Amarnath,

The local capacitance next to PMIC should not exceed 4uF, i would recommend it changing it to default 2.2uF. There could be additional capacitance at the point of load and a maximum if 20uF is supported.

Sathish 

AMARNATH G said:

So, Pulling Up the I2C lines to Buck2 output shall not have any issues regarding the I2C communication with AM6442 later, correct?

Also, from the power sequencing point of view also we shall not have any issues later. 

Is my understanding correct?

That is correct. It is okay to pull up I2C lines to Buck2 output.

Amarnath,

Please refer to data sheet Table 8-1 for the recommended output capacitance. As mentioned before, if PCB size allows, it is always recommended to have higher capacitance within the recommended range.

Sathish

HI Sathish,

Since we are not using LDO1 & LDO4 outputs in our design, is there any possibility to remove the output capacitor on LDO1 & LDO4 output? Since we don't have a space on the board, we literally want to remove those output capacitors on LDO1 & LDO4 outputs. Kindly provide your comments on the same to remove the decaps on LDO1 & LDO4 rail or any other work around.

Regards'

Amarnath G 

Hi Amarnath,

If LDO output cap is missing, the output could be oscillating and UV fault could shutdown the PMIC.

It is okay with no output caps when LDO is disabled but these are used in power sequence.

Sathish

Hi Sathish,

Since we are using TPS6522053RHBR PMIC and also, we are using TLV75533PDQNR (3.3V LDO) from TI.

Here in our design, we want to enable and disable the LDO TLV75533PDQNR through PMIC GPO2 pin.

But the challenge we face here is that the Vol of GPO2 pin of PMIC TPS6522053RHBR is 0.4V max and the VLO for EN pin is 0.3V max. Here since there is a difference of 0.1V will there be an issue if we want to disable the LDO?

Can you please provide your comments on the same.

Thank you.

Regards
Amarnath G