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TPS23881: Parity and SRAM programming via Linux driver (kernel 6.1)

Renjith I S
Prodigy 10 points
Part Number: TPS23881
Other Parts Discussed in Thread: TPS23880

Tool/software:

Hi,
I am trying to enable this IC to provide 60W of power to another device. I am able to get it to work in low power mode and the PD is able to boot. When PD is trying to draw more power, PSE stops giving power. I am of the understanding that I need to send SRAM data to the IC to enable >30W power delivery.

I have ported the upstream driver(6.12) found below to my kernel (6.1)
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/net/pse-pd/tps23881.c?h=v6.12.12

In the probe function, parity and SRAM flash is initiated and the I2C write is successful (both the ~20KB parity and 180KB SRAM), but the firmware revision is read as 0xFF (I am using TPS23881_2_PARITY_v15 & TPS23881_2_SRAM_v15 bin files)

I have added printk to i2c write function for 0x20 to see what all data is being sent to the chip

Here is the debug info when using v15 of parity and SRAM. Getting tps23881 2-0020: Firmware revision 0xff instead of 0x15

root@...-board:~# insmod tps23881_6.12_ref_v15.ko
[   29.829113] kernel_read_file_from_path_initns path=/lib/firmware/TPS23881_2_PARITY_v15.bin
[   29.838140] ... tps: i2c_smbus_write_byte_data addr:20 reg:60 data:01
[   29.844950] ... tps: i2c_smbus_write_byte_data addr:20 reg:62 data:00
[   29.851681] ... tps: i2c_smbus_write_byte_data addr:20 reg:63 data:80
[   29.858380] ... tps: i2c_smbus_write_byte_data addr:20 reg:60 data:c4
[   29.865081] ... tps: i2c_smbus_write_byte_data addr:20 reg:1d data:bc
[   29.871775] ... tps: i2c_smbus_write_byte_data addr:20 reg:d7 data:02
[   29.878474] ... tps: i2c_smbus_write_byte_data addr:20 reg:91 data:00
[   29.885175] ... tps: i2c_smbus_write_byte_data addr:20 reg:90 data:00
[   29.891873] ... tps: i2c_smbus_write_byte_data addr:20 reg:d7 data:00
[   29.898573] ... tps: i2c_smbus_write_byte_data addr:20 reg:1d data:00
[   31.530767] kernel_read_file_from_path_initns path=/lib/firmware/TPS23881_2_SRAM_v15.bin
[   31.541516] ... tps: i2c_smbus_write_byte_data addr:20 reg:60 data:c5
[   31.548243] ... tps: i2c_smbus_write_byte_data addr:20 reg:62 data:00
[   31.554942] ... tps: i2c_smbus_write_byte_data addr:20 reg:63 data:80
[   31.561635] ... tps: i2c_smbus_write_byte_data addr:20 reg:60 data:c0
[   31.568333] ... tps: i2c_smbus_write_byte_data addr:20 reg:1d data:bc
[   31.575020] ... tps: i2c_smbus_write_byte_data addr:20 reg:d7 data:02
[   31.581716] ... tps: i2c_smbus_write_byte_data addr:20 reg:91 data:00
[   31.588413] ... tps: i2c_smbus_write_byte_data addr:20 reg:90 data:00
[   31.595106] ... tps: i2c_smbus_write_byte_data addr:20 reg:d7 data:00
[   31.601805] ... tps: i2c_smbus_write_byte_data addr:20 reg:1d data:00
[   38.291518] kauditd_printk_skb: 3 callbacks suppressed
[   38.291528] audit: type=1334 audit(1677930006.820:21): prog-id=10 op=UNLOAD
[   38.305693] audit: type=1334 audit(1677930006.820:22): prog-id=9 op=UNLOAD
[   45.818518] ... tps: i2c_smbus_write_byte_data addr:20 reg:60 data:18
[   45.837342] tps23881 2-0020: Firmware revision 0xff
[   45.842349] ... tps: i2c_smbus_write_byte_data addr:20 reg:17 data:a0
[   45.849067] i2c_smbus_write_word_data addr:20 reg:26 data:e4e4
[   45.855012] i2c_smbus_write_word_data addr:20 reg:12 data:aaaa
[   45.860954] i2c_smbus_write_word_data addr:20 reg:13 data:0000
[   45.866895] i2c_smbus_write_word_data addr:20 reg:29 data:0000
[   45.872846] i2c_smbus_write_word_data addr:20 reg:14 data:0000
[   45.879745] tps23881 2-0020: DebugFS entry registers created
[   45.885465] ... tps: DebugFS entry registers created

Here is the debug info when using v14 of parity and SRAM. Getting tps23881 2-0020: Firmware revision 0x0 instead of 0x85

root@...-board:~# insmod tps23881_6.12_ref_v14.ko
[  277.778863] kernel_read_file_from_path_initns path=/lib/firmware/TPS23881_2_PARITY_v14.bin
[  277.787623] ... tps: i2c_smbus_write_byte_data addr:20 reg:60 data:01
[  277.794385] ... tps: i2c_smbus_write_byte_data addr:20 reg:62 data:00
[  277.801107] ... tps: i2c_smbus_write_byte_data addr:20 reg:63 data:80
[  277.807816] ... tps: i2c_smbus_write_byte_data addr:20 reg:60 data:c4
[  277.814521] ... tps: i2c_smbus_write_byte_data addr:20 reg:1d data:bc
[  277.821216] ... tps: i2c_smbus_write_byte_data addr:20 reg:d7 data:02
[  277.827916] ... tps: i2c_smbus_write_byte_data addr:20 reg:91 data:00
[  277.834612] ... tps: i2c_smbus_write_byte_data addr:20 reg:90 data:00
[  277.841349] ... tps: i2c_smbus_write_byte_data addr:20 reg:d7 data:00
[  277.848052] ... tps: i2c_smbus_write_byte_data addr:20 reg:1d data:00
[  279.495612] kernel_read_file_from_path_initns path=/lib/firmware/TPS23881_2_SRAM_v14.bin
[  279.506359] ... tps: i2c_smbus_write_byte_data addr:20 reg:60 data:c5
[  279.513106] ... tps: i2c_smbus_write_byte_data addr:20 reg:62 data:00
[  279.519809] ... tps: i2c_smbus_write_byte_data addr:20 reg:63 data:80
[  279.526512] ... tps: i2c_smbus_write_byte_data addr:20 reg:60 data:c0
[  279.533209] ... tps: i2c_smbus_write_byte_data addr:20 reg:1d data:bc
[  279.539906] ... tps: i2c_smbus_write_byte_data addr:20 reg:d7 data:02
[  279.546604] ... tps: i2c_smbus_write_byte_data addr:20 reg:91 data:00
[  279.553307] ... tps: i2c_smbus_write_byte_data addr:20 reg:90 data:00
[  279.559999] ... tps: i2c_smbus_write_byte_data addr:20 reg:d7 data:00
[  279.566691] ... tps: i2c_smbus_write_byte_data addr:20 reg:1d data:00
[  293.784973] ... tps: i2c_smbus_write_byte_data addr:20 reg:60 data:18
[  293.804701] tps23881 2-0020: Firmware revision 0x0
[  293.809627] ... tps: i2c_smbus_write_byte_data addr:20 reg:17 data:a0
[  293.817623] i2c_smbus_write_word_data addr:20 reg:26 data:e4e4
[  293.823595] i2c_smbus_write_word_data addr:20 reg:12 data:aaaa
[  293.829557] i2c_smbus_write_word_data addr:20 reg:13 data:0000
[  293.835523] i2c_smbus_write_word_data addr:20 reg:29 data:0000
[  293.841467] i2c_smbus_write_word_data addr:20 reg:14 data:0000
[  293.856116] tps23881 2-0020: DebugFS entry registers created
[  293.861823] ... tps: DebugFS entry registers created

In both cases, the firmware seems to be getting rejected by the IC. I have re-downloaded the firmware and rechecked to make sure the firmware files are not corrupted.

Any advice to resolve this will be appreciated.

  • 0
    TI__Expert 6851 points

    Hi,

    Our PoE team is currently out of office and will be back tomorrow. Sorry for the delay.,

    BR,

    Ke Wang

  • 0 in reply to Ke Wang
    Prodigy 10 points

    Can anyone tell me what might be going wrong with the parity and SRAM data?
    the functions in the driver code are like this:

    static const struct tps23881_fw_conf tps23881_fw_parity_conf[] = {
{.reg = 0x60, .val = 0x01},
{.reg = 0x62, .val = 0x00},
{.reg = 0x63, .val = 0x80},
{.reg = 0x60, .val = 0xC4},
{.reg = 0x1D, .val = 0xBC},
{.reg = 0xD7, .val = 0x02},
{.reg = 0x91, .val = 0x00},
{.reg = 0x90, .val = 0x00},
{.reg = 0xD7, .val = 0x00},
{.reg = 0x1D, .val = 0x00},
{ /* sentinel */ }
};

static const struct tps23881_fw_conf tps23881_fw_sram_conf[] = {
{.reg = 0x60, .val = 0xC5},
{.reg = 0x62, .val = 0x00},
{.reg = 0x63, .val = 0x80},
{.reg = 0x60, .val = 0xC0},
{.reg = 0x1D, .val = 0xBC},
{.reg = 0xD7, .val = 0x02},
{.reg = 0x91, .val = 0x00},
{.reg = 0x90, .val = 0x00},
{.reg = 0xD7, .val = 0x00},
{.reg = 0x1D, .val = 0x00},
{ /* sentinel */ }
};

static int tps23881_flash_sram_fw_part(struct i2c_client *client,
const char *fw_name,
const struct tps23881_fw_conf *fw_conf)
{
const struct firmware *fw = NULL;
int i, ret;

ret = request_firmware(&fw, fw_name, &client->dev);
if (ret)
return ret;

dev_dbg(&client->dev, "Flashing %s\n", fw_name);

/* Prepare device for RAM download */
while (fw_conf->reg) {
ret = i2c_smbus_write_byte_data(client, fw_conf->reg,
fw_conf->val);
if (ret)
goto out;

fw_conf++;
}

/* Flash the firmware file */
for (i = 0; i < fw->size; i++) {
ret = i2c_smbus_write_byte_data(client,
TPS23881_REG_SRAM_DATA,
fw->data[i]);
if (ret)
goto out;
}

out:
release_firmware(fw);
return ret;
}

static int tps23881_flash_sram_fw(struct i2c_client *client)
{
int ret;

ret = tps23881_flash_sram_fw_part(client, fw_parity_name,
tps23881_fw_parity_conf);
if (ret)
return ret;

ret = tps23881_flash_sram_fw_part(client, fw_sram_name,
tps23881_fw_sram_conf);
if (ret)
return ret;

ret = i2c_smbus_write_byte_data(client, TPS23881_REG_SRAM_CTRL, 0x18);
if (ret)
return ret;

mdelay(12);

return 0;
}
  • 0
    Prodigy 10 points

    I have also tried to send data to the i2c bus from linux user space using i2c-tools. This is the resulting script and it does not work as well. (~200 line script)

    https://smalldev.tools/share-bin/VMcXi66f
    Alternate link : https://codefile.io/f/fJd27Ug92b

    It also results in 0x41 to be 0xff after sram load

    Config for parity load
i2cset -y "2" "0x20" "0x60" "0x01" b
i2cset -y "2" "0x20" "0x62" "0x00" b
i2cset -y "2" "0x20" "0x63" "0x80" b
i2cset -y "2" "0x20" "0x60" "0xC4" b
i2cset -y "2" "0x20" "0x1D" "0xBC" b
i2cset -y "2" "0x20" "0xD7" "0x02" b
i2cset -y "2" "0x20" "0x91" "0x00" b
i2cset -y "2" "0x20" "0x90" "0x00" b
i2cset -y "2" "0x20" "0xD7" "0x00" b
i2cset -y "2" "0x20" "0x1D" "0x00" b
Loading Parity firmware...
Loading firmware: /lib/firmware/TPS23881_2_PARITY_v15.bin (20649 bytes)
Progress: 99% (20448/20649 bytes)
Firmware /lib/firmware/TPS23881_2_PARITY_v15.bin loaded successfully!
Config for SRAM load
i2cset -y "2" "0x20" "0x60" "0xC5" b
i2cset -y "2" "0x20" "0x62" "0x00" b
i2cset -y "2" "0x20" "0x63" "0x80" b
i2cset -y "2" "0x20" "0x60" "0xC0" b
i2cset -y "2" "0x20" "0x1D" "0xBC" b
i2cset -y "2" "0x20" "0xD7" "0x02" b
i2cset -y "2" "0x20" "0x91" "0x00" b
i2cset -y "2" "0x20" "0x90" "0x00" b
i2cset -y "2" "0x20" "0xD7" "0x00" b
i2cset -y "2" "0x20" "0x1D" "0x00" b
Loading SRAM firmware...
Loading firmware: /lib/firmware/TPS23881_2_SRAM_v15.bin (180394 bytes)
Progress: 99% (178592/180394 bytes)
Firmware /lib/firmware/TPS23881_2_SRAM_v15.bin loaded successfully!
Finish SRAM load
i2cset -y "2" "0x20" "0x60" "0x18" b
SRAM Load Failed. Entering Safe Mode!

  • 0 in reply to Renjith I S
    TI__Mastermind 37121 points

    Hi Renjith,

    Thanks for reaching out!

    The reply may be delayed due to the limited resource and Lunar New Year. We will get back to you in two weeks. Thanks for your patience! 

    Best regards,

    Diang

  • 0 in reply to Diang Xing
    Prodigy 10 points

    Any kind of direction I should look into would be helpful

  • 0 in reply to Renjith I S
    TI__Mastermind 37121 points

    Hi Renjith,

    Thanks for your patience. I am not sure if TI's published code in Secure resources is complaint with Linux or not. It marked as Windows. 

    Could you try with a Windows System? We have a video of loading SRAM code for TPS23880, which is close to TPS23881 (https://www.ti.com/video/series/power-over-ethernet-poe-training-series.html)

    Best regards,

    Diang

  • 0 in reply to Diang Xing
    Prodigy 10 points

    We used a windows system to install the .exe and got the .bin files from the installed folder.
    The md5sum of parity and SRAM files are as follows:

    md5sum *.bin
340f54029aa084bb822788663dd13616 TPS23881_2_PARITY_v15.bin
a2f7111bf7e2f3d181ee59bb45a62d6e TPS23881_2_SRAM_v15.bin

  • 0 in reply to Renjith I S
    TI__Mastermind 37121 points

    Hi Renjith,

    Yes, you will need load both SRAM and PARITY code 

    Best regards,

    Diang

  • 0 in reply to Diang Xing
    Prodigy 10 points

    Hi Diang Xing,
    We are loading PARITY first and then SRAM
    Files are located in the target system (i.MX93 Linux kernel 6.1 (modified with TPS23881 driver)) at

    /lib/firmware/TPS23881_2_PARITY_v15.bin

    /lib/firmware/TPS23881_2_SRAM_v15.bin

    With how the driver is written, it uses firmware_loader (ret = request_firmware(&fw, fw_name, &client->dev);) to read the file. it will check some locations in /lib/firmware. If you look at the code, the file read and i2c writes are successful.

    I have added prints to all commands that are sent to i2c writes (Opening post).

  • 0 in reply to Renjith I S
    TI__Mastermind 37121 points

    Hi Renjith,

    Thanks for your updates.

    TI may not cover the PSE SRAM portfolio for all types of systems. The system may be different but hope the SRAM and PARITY can be loaded. Please let us know if you have other questions or concerns. 

    Best regards,

    Diang