TPS65219: Start Up Time of VSYS(5V)

Hi Shinichi,

Thank you for reaching out on E2E.

The minimum 2.5V requirement on SYS is coming from VSYSPOR threshold, that would be the minimum voltage on VSYS for the device to transition from OFF state.

Once Vsys reached this voltage, it takes about 2.3ms for the device to load EEPROM values into the registers.

On TPS6521901 version, FSD is set to 1 so it ignores EN on the first power up only.

Sathish

Hi Sathish,

Thank you for your reply.

Sathish Vallamkonda said:

Once Vsys reached this voltage, it takes about 2.3ms for the device to load EEPROM values into the registers.

Does this mean that it is not a problem if VSYS rises slowly?

Thank you for sending me your friendship.

I'll share the file with offline.

Could you please see and advise?

I appreciate your great help and cooperation.

Best regards,

Shinichi

Hi Shinichi,

That is correct. I tried with 100mV/s and it powered up fine.

Sathish

Hi Sathish,

I sent your answer to the customer.

The customer has additional questions, could you please advise.

---Questions

(1) If VSYS rises slowly, the PMIC output (3.3V) will start up once, then drop and start up again (depending on the rise speed).

In addition, when it is extremely slow, it will try to start up three times and fail, and then never start up again.

It depends on the specs of the IC that generates the VSYS in the previous stage, I think it is a problem if it rises slowly.

I shared the start up waveform in the private message.

(2) I don't think it makes sense for EN to be ignored by default. Is this a PMIC errata?

(3) Is my understanding correct？

When using a PMIC, since it cannot be controlled by EN.

The power supply in the previous stage of VSYS needs to start up quickly

Also, specifically, within how many msec does VSYS start up have to be before it affects the start-up of the PMIC output?

---

I appreciate your great help and cooperation.

Best regards,

Shinichi

Hi Shinichi,

With FSD enabled, PMIC ignores EN on the first power up only and when VSYS rises above 2.5V, PMIC tries to start power up sequence and the first rail powering up will show 3 voltages peaks (1 power up + 2 retries) but since the VSYS voltage is not high enough the rail shuts down.

But, once VSYS reaches full 5V, then when EN goes high it will have normal power up.

Can you please ask customer to take EN from low to high (or toggle) after Vsys reached 5V and check the power up sequence?

Sathish

HI Sathish,

Thank you for your reply.

I'll share your suggestion with the customer.

When I obtain the feedback, I'll share with you.

I appreciate your great help and cooperation.

Best regards,

Shinichi

Sure Shinichi.

Hi Sathish,

The customer has an additional question.

Could you please advise?

---

Could you please let me know what is the maximum VSYS rise time for the TPS6521901 to start up normally in msec?

As you mentioned before, there is no problem if EN is made active after VSYS (5V) has started up, but it is difficult to achieve that with our products.
- Even if we try to control it with the SoC's GPIO, it's impossible because the PMIC isn't started.
-I understand that it is possible to add a hardware voltage detector to monitor 5V. However, if the power is cut off or the 5V drops slightly, the PMIC will immediately turn off, so backup processing will not be possible, and this cannot be adopted.

Therefore, I understand that the only solution is to start it up quickly within the maximum VSYS rise time.
---

I appreciate your great help and cooperation 

Best regards,

Shinichi

Hi Sathish,

Thank you for your reply.

I'll share this information with the customer.

When the customer has an additional question, could you please advise.

I appreciate your great help and cooperation.

Best regards,

Shinichi