• State Resolved
  • +1 person also asked this people also asked this
  • Locked Locked
  • Replies 5 replies
  • Subscribers 65 subscribers
  • Views 153 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCC39002: The Principle of Control Mode

Francis Jiang
Expert 3260 points
Part Number: UCC39002

Tool/software:

Hi Team,

Customer would like to know whether the host ADJ output will change to 0 after other slave ADJs finished current sharing control?

BRs,

Francis

  • +1
    TI__Mastermind 40520 points

    Hello Francis, 

    Please inform your customer to be aware that there is no fixed "host" module (also known as "master" or (now) "leader") with all other modules being "slaves" (or (now) "followers").

    Any one of the N modules involved with current-sharing can become the leader module depending only on which module happens to be delivering the highest output current at any given moment.  All other modules are delivering lower current to the load and are by definition followers. 
    The leader module, by definition, has its ADJ current = 0.  The leader does not have to make any changes to its respective converter, because it is already putting out more than its share of the total current. 

    The load-share controllers in each follower are all sinking some variable amount of ADJ current > 0A to adjust the feedback signal of their respective power converters.  
    This ADJ current is always > 0 to make their feedback look lower so as to raise their respective output voltage higher to raise their respective output current higher to match the leader's current. 

    Of course, if all of N modules put out the same current as the leader, which already started with more than its share of the load, then there would be too much current for the load and the system Vout would rise.  In this case, the normal converter feedback loop would sense the Vout increase and reduce duty cycle to reduce output current to keep Vout regulated.  So the leader module's current will also decrease even while the followers currents are increasing, until all modules' currents "meet in the middle" and are approximately equal.  

    For this to be successful, the load-share loop response must be 1/10 or less of that of each module's voltage loop response. 
    This way, the voltage loops can maintain Vout regulation and their usual transient response, while the current loops are slowly adjusting to achieve and maintain equal load-sharing.  The current loops should be slow enough to not interfere with the voltage loops. 

    Note that while the currents are adjusting, it typical that the module that started out as the leader stays the leader when steady-state is reached.  However it is possible that during the dynamic adjustment period, some other module may take over as leader and the previous leader becomes a follower.   This is mostly possible during dynamic load transients where the various modules may react to the load transient with slightly different response times.   
    In theory, all modules are identical in design and behavior, but in reality there are always slight differences.   Tight sharing during transients should not be expected.  

    To reiterate the answer to the original question:
    The leader module's ADJ current is already 0 before the followers finish adjusting their sharing levels, but the leader may or may not remain the leader by the time all of the adjustments have been completed in steady-state operation. 

    Regards,
    Ulrich

  • 0 in reply to Ulrich Goerke
    TI__Intellectual 2781 points

    Hi Ulrich,

    Many thanks to the detailed explanation!

    Ulrich Goerke said:
    n this case, the normal converter feedback loop would sense the Vout increase and reduce duty cycle to reduce output current to keep Vout regulated.  So the leader module's current will also decrease even while the followers currents are increasing, until all modules' currents "meet in the middle" and are approximately equal.  

    For all modules to meet in the middle, they need to reduce their respective current proportionally. Other wise, some modules would decrease too fast that it gives up all load and let other module took over it.

    Is there any algorithm, like DC droop control, used in this process to ensure this?

    Regards,

    Hang.

  • +1 in reply to Hang Yang
    TI__Mastermind 40520 points

    Hello Hang, 

    There is no algorithm nor droop control in this process. 

    As I mentioned above, the load-sharing loop response should be at least 10 times slower than the voltage loop response. 
    That way, when the V-loop of all modules start reducing their respective output voltages, all modules' currents also begin to reduce in the same proportion. 

    The slower current loops will still work to meet in the middle as they have before, but the "middle" is also effectively dropping with the voltage loop response. 
    So the currents have plenty of time to settle toward the new middle without disturbing the output voltage.

    The voltage loops of the modules will change all of the modules' currents quickly as the load changes, however the ratio of sharing adjusts itself slowly to a steady-state.

    Regards,
    Ulrich

  • 0 in reply to Ulrich Goerke
    TI__Intellectual 2781 points

    Hi Ulrich,

    Ulrich Goerke said:
    The voltage loops of the modules will change all of the modules' currents quickly as the load changes, however the ratio of sharing adjusts itself slowly to a steady-state.

    I still have confusion on the process of the slow sharing adjustment. Maybe I can ask in another way. What's the I-V characteristic of the module when the fast loop reach steady?

    If there's no droop control, output voltage is independent of output current. Then the I-V characteristic would be a flat line. When we want to find the operating point of a parallel modules, we plot their I-V characteristic together and draw another flat line to find the intersections. If the characteristic is flat, there would be no intersection. Therefore, the characteristic should not be a flat line.

    Regards,

    Hang. 

  • +1 in reply to Hang Yang
    TI__Mastermind 40520 points

    Hello Hang, 

    The I-V characteristics of the power supply modules are not absolutely flat lines, but they have minimal finite slope. 
    The ADJ function of the UCC39002 adjusts the voltage feedback of each module to move the nearly-flat lines of multiple modules together. 

    These two papers may help explain the load-sharing (LS) concept of the UCC39002.  They were written many years ago for older versions of the LS controller, but the basic concepts are still the same even though some of the implementation is different. 

    https://www.ti.com/lit/pdf/slua147

    https://www.ti.com/lit/pdf/slua128

    Regards,
    Ulrich