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UCC21750QDWEVM-054: UCC21750QDWEVM-054

Rahman Sajadi
Prodigy 50 points
Part Number: UCC21750QDWEVM-054

Tool/software:

Hi,

I am using the UCC21750QDWEVM-054. Looks like the peak output current depends on the load capacitor, and it will increase the current by increasing the output capacitance. For instance, the output current is around 3A for Cload=9nF and it is almost 10A for Cload=100nF. I have added the buffer stage by adding the BJT or MOSFET and it didn't change the output current even for higher capacitance and it is limited to 10A (It is supposed to go up to 30A with the buffer stage). I want to have the peak output current with low load capacitor as well and I would be grateful if you tell me how to configure the gate driver in this case and finally go to 30A with buffer stage for low output capacitor (For instance 10nF).

Thanks,

  • 0
    TI__Expert 6670 points

    Hi Rahman, 

    With the buffer stage, what gate resistances are you using? The peak current when using the buffer stage will be affected by the external gate resistance on the EVM as well as the internal gate resistance of the power switch you're driving, though looks like you're just driving a load capacitor. Also keep in mind that the voltage across Cload also affects the peak current; as Cload gets charged up, the current will decrease because of the effects of the gate resistor and internal FET pull-up resistance. In your case, for Cload = 9nF, the peak current has not reached 10A before it starts decaying, while in the case of Cload = 100nF, peak current was able to reach 10A before decaying. 

    I would recommend first removing any external gate resistor in the gate loop when using the buffer stage, like R79 and R86. Then, try out larger Cload to see if it's possible to reach 30A. You can also increase VDD for potentially higher peak current with the buffer stage. 

    Thanks, 

    Vivian

  • 0 in reply to Vivian Qi
    Prodigy 50 points

    Hi Vivian,

    Thanks for you reply. I have removed the R81 and R85 and populated them on R79 and R86 for buffer stage. Sorry, I could not understand how the buffer stage works by removing R79 and R86. In this case there no connection from BJT emitter to the gate of device under test. Brw, I need to have high current output for any output capacitors. 

    Thanks,

  • 0 in reply to Rahman Sajadi
    TI__Expert 6670 points

    Hi Rahman, 

    I meant changing the R79 and R86 to 0 ohms - no gate resistances. Sorry if it's unclear. 

    Vivian

  • 0 in reply to Vivian Qi
    Prodigy 50 points

    Hi Vivian,

    I changed the resistors to 0 ohms and increased the Vdd. I could reach to 17.5A for Cload=45nF which is fine for my application. I have only one concern right now and that is the switching frequency. The switching frequency should be at least 50KHz but the output gate pulse will get noise and if I increase the fs further the LED (RDY) is on and output gate pulse will be off. Do you have any suggestions to fix that problem? Do you think it is due to thermal issue in the gate driver?

    Thanks,

  • 0 in reply to Rahman Sajadi
    TI__Expert 6670 points

    Hi Rahman, 

    With a buffer stage in place, thermal should not be an issue for the gate driver. I think the limitation comes from the on-board bias supply. When you're driving a large load with high peak current and high switching frequency, it draws a lot of power from the isolated bias supply on the board, which can make VDD unstable. With the VDD dropping below UVLO, RDY will be pulled low and output will be turned off. 

    You can try powering the secondary side with a bench power supply instead of using the on-board bias supply. I would recommend un-populating the LLC converter components to prevent any damage. 

    Thanks, 

    Vivian