TPS6594-Q1: PGOOD feature

Koshi Ninomiya said:

Since the functional safety is not needed, they are going to disable the ESM as default. So, there is no connection between the TPS6594-Q1 and the DRA821-Q1 as show below.
<No connection>
    - from DRA821 (SOC_SAFETY_ERRORn) into TPS6594-Q1 (GPIO_3 (nERR_SOC))
    - fromDRA821 (MCU_SAFETY_ERRORn) into TPS6594-Q1 (GPIO_7 (nERR_MCU))

On the PMIC side, the ESMs disabled by default. So it is ok to leave these pins floating.

Koshi Ninomiya said:

Under the above condition, they would like to reset the system when each power supply lane of the TPS6594-Q1 is out of the range of PGOOD.
Is it possible?

If a PMIC rail goes beyond the OV/UV thresholds of Table 5-4 and 5-5, an MCU_PWR_INT or SOC_PWR_INT will trigger according to the rail power groups in Table 5-8. If an SOC rail has a fault then only the SOC rails will turn off, while an MCU rail fault will cause the PMICs to power cycle. If you want the same behavior for all rails, change the SOC_RAIL_TRIG bit field to 0x2 on both devices.