TPS7H5006-SEP: Trouble with unencrypted SPICE model

Hey David,

Is there the same issue with the TPS7H5001-SP model?
Sometimes updates that happen with that family of models happen with the TPS7H5001-SP first before they are done to the other devices.

Which simulator are you using to test the device?
What does your schematic look like?

Thanks,
Daniel

Same trouble comes from the TPS7H5001 model.  I'm using MicroCap12, 64 bit. Sorry my group cant settle on buying a new SPICE simulator.

P.S. The TPS7H5001 model has numerous lines with only line feeds at the end and no carriage returns.  MicroCap does not interpret the line feed only as an end of a line, and so concatenates these lines with the lines below them.  The other two models did not have this problem.

Hi David,

Can you confirm that the max step size has been defined in your sim settings and, if so, what it is set to? Also, when you comment out line 712 in the 5002 model does that resolve the problem you were encountering, or does the problem persist? I can sanity check that portion of the circuit and see if there is anything that stands out as a possible cause.

Is using PSpice-for-TI an option for you in the meantime? The download is entirely free and would allow you to avoid issues that are directly related to SPICE simulation tool differences.

Thanks,

Sarah

I have run maximum step sizes from 10 ns down to 0.25 ns.  I can get it to switch if I just force the COMP pin with a low impedance source, and depending on how hard I'm driving the switch, I need that 0.25 ns.  Unfortunately even when I drive the COMP pin, the clock behaves strangely with varying frequencies and the occasional extra pulse. 

Commenting out line 712 in the 5002 model makes it behave the same as the 5006 model.  No SS current, weird clock behavior when driving the COMP pin to force switching behavior.

A coworker has now tried the model in LT spice, and the SS pin behaves, but it only ever gives a 50% duty cycle.  I might have to struggle with IT to get PSPICE-for-TI.

Thanks David, appreciate the additional details.

For this family of devices I would recommend a 20ns max step size as noted in the netlist file. 

There is one netlist alteration I would like you to try. As Daniel mentioned, the TPS7H5001-SP model will often receive updates before the remaining models for this family of devices. There is a clock bug that was fixed in that model by adding the following line to the model netlist:

X_U117 SYS_CLOCK N16649359 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=20n

Can you let me know if setting the max step size to 20ns and adding this line to the unaltered version of the netlist that is published to TI.com improves or resolves the switching/clock challenges?

As a heads up, Monday is a holiday. Daniel or myself will get back to you with further support on Tuesday if needed.

Thanks,

Sarah

Hi Sarah,

Adding in that line on LT SPICE did not fix the issue of always driving at either 0% or 50% duty cycle.  Neither did adding that line and changing the maximum step size to 20 ns.  The new line of code did not make the soft start function work in MicroCap.  However, when forcing a duty cycle by directly driving the COMP pin in MicroCap, it has resolved the erratic clock behavior.  Currently my MicroCap simulation does not converge for minimum step sizes greater than about 10 ns.

I'm still working with IT about installing PSPICE.  I'll also see if the new line of code opens up something I've been missing in MicroCap.

Hey David,

Forcing the COMP pin should have no effect on the clock, which would point towards issues with the simulator.

While I dont know your full schematic I am also suspicious of some of the values you posted in your picture.
We can try simulating your schematic in our PSPICE for TI simulator so that we can try and separate what might be multiple issues.
How much of your schematic are you able to share?

Thanks,
Daniel

Daniel,

Forcing the comp pin is the only way I get any switching in MicroCap.  Prior to the new line of code there was erratic behavior from the clock, but now there isn't.  I probably didn't pay much attention to the clock (SYNC pin) when there was no switching output, so the erratic behavior was probably there whether I drove the COMP pin or not. 

There's not much more than what I showed in the earlier screen grab.  We're still in a very preliminary design phase.  I threw my thumb in the wind for a lot of this.  I just want to get a good grasp on the part's behavior, like how soft start works.  The design of the power supply itself is the easy part.

Hey David,

What are the values of the capacitors labeled X?

Thanks,
Daniel

Non polarized capacitors with sub-circuit models are 47 nF, CDR35 ceramic capacitors.  Polarized capacitors with sub-circuit models are 330 uF polymer tantalum.

Hey David,

ESR of the polymer tantalum capacitors have a large effect on the simulation.
Would you be able to provide that value?

Thanks,
Daniel

Kemet part number is T541X337K016AT.  I don't know why the sub-circuit model started with pins 1 and 8 instead of pins 1 and 2, but I never bothered changing it.  Here's the whole thing:

.SUBCKT T541X337K016AT 1 8
*Temp = 25°C, Bias = 3.3VDC, Center Frequency = 10000 Hz
*KEMET Model RLC Tant5RC
R1 2 3 0.004076345823705196
R2 3 4 0.0012731727911159396
R3 4 5 0.0012731727911159396
R4 5 6 0.0012731727911159396
R5 6 7 0.0012731727911159396
R6 2 8 30300
L1 1 2 2.4999999848063226E-09
C1 3 8 1.064516129032258E-05
C2 4 8 2.129032258064516E-05
C3 5 8 4.258064516129032E-05
C4 6 8 8.516129032258064E-05
C5 7 8 0.00017032258064516128
.ENDS

Sorry, here's one at 300 kHz if you really want to be precise...

.SUBCKT T541X337M016AT 1 8
*Temp = 25°C, Bias = 0VDC, Center Frequency = 300000 Hz
*KEMET Model RLC Tant5RC
R1 2 3 0.004228060173122035
R2 3 4 0.0013490301815662449
R3 4 5 0.0013490301815662449
R4 5 6 0.0013490301815662449
R5 6 7 0.0013490301815662449
R6 2 8 30300
L1 1 2 2.386226577091086E-09
C1 3 8 1.064516129032258E-05
C2 4 8 2.129032258064516E-05
C3 5 8 4.258064516129032E-05
C4 6 8 8.516129032258064E-05
C5 7 8 0.00017032258064516128
.ENDS

Hey David,

I assume VIN is 28 V?

The part number will let me estimate things to a point I can run something overnight in PSPICE for TI.

Thanks,
Daniel

Hey David,

After running a couple of simulations, the values picked are definitely causing some of the issue.

I can help give guidance if you want to share your expectations of the performance of the converter.
If you can get your IT group to let you download PSPICE for TI, we have a working schematic online that is a flyback converter you can use as a basis for your simulations.

Thanks,
Daniel

Causing it to not charge the soft start capacitor?

Yes, 28 V.

Hey David,

The device not charging the SS cap would seem to be a simulator specific issue.
I am able to get the device to "turn on"
The behavior I am talking about would be the instability of the part.

Thanks,
Daniel

Ah.  The LT SPICE simulation isn't exactly the same as this one.  We have a high confidence that problem isn't stability, or at least not the stability alone, because no matter what we set the max duty cycle to, we only get 50% or zero, and it switches between the two immediately, not even one cycle of an intermediate duty cycle.  We might as well switch to doing the compensation design since we can't check things like wake-up on this new chip in simulation right now.  I'll let you know what comes out of that.

I know you have a process, and probably a marketing agreement, but putting quick and easy features in the model that only certain simulators can run (like TD in a switch model) is frustrating.  TI likes PSPICE, Intersil likes SIMPLIS.  I can't just pick one because one supplier prefers it.

Hey David,

We have both PSPICE models and SIMPLIS models.
You are free to use either because we use both internally.
There is some problem with PSPICE simulators because each simulator likes to accept slightly different nomenclature which can cause conflicting issues.
This is why we try and provide a free version of PSPICE we can officially support.

The PSPICE model last time we checked did run properly in LTSPICE.
Sarah was trying to step you through the process that allowed the device to work in LTSPICE as well as a small bug fix.
The constant switching between different issues has been getting confusing.
I am trying to build a working schematic to build off of so that each of these issues can be addressed separately.

Thanks,
Daniel

I missed the SIMPLIS stuff.  That might help for future decisions.  Thanks.

We mixed up some rules of thumb between DCM and CCM designs in our SPICE simulations, but even with doing a full frequency response design, LT SPICE has either 0 or 50 % duty cycle, and MicroCap wont charge the soft start capacitor.  You said it worked in LT spice at one point.  Do you have something you can share?

Hi David,

Daniel is out today. Let me see if I am able to recreate the issues you described. 

Thanks,

Sarah

Hi David,

Using your design values, I'm not seeing any instances where the duty cycle is getting stuck at 0 or 50% pulses or where the soft start cap isn't being charged. I tested using a simple switch+diode instead of primary FET and also provided VIN with a voltage source instead of the circuitry you're using - this was mainly to reduce the possible issues those components themselves could be introducing to the simulation for now.

My guess is that MicroCap can't recognize parameters and needs the soft start current and threshold passed in as hard-coded values (SS_thresh=1 & I_ss=2.7u, as well as EA_gm=1800u). You could try searching for those parameters in the netlist file and replacing them with the hard-coded values and see if that resolves the charging issue in MicroCap, but if not I'm uncertain what the issue with that simulator would be. 

I also forgot to mention another step needed for the netlist alteration if using the 5006 model. You could use the 5001 model and connect the unused pins to a 1k resistor to GND as well, which may be a less error-prone method. 

1. Add this line to the netlist as stated originally: X_U117 SYS_CLOCK N16649359 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=20n
2. Alter this line: X_U42 BLANK NOT_BLANK SYS_CLOCKN16649359 DIG_HI N16649275 DIG_HI DFFSBRB_RHPBASIC_GEN_BLANK PARAMS: VDD=1 VSS=0 VTHRESH=0.5

Sorry for the long post, but please let us know if this corrects the main issues you're seeing. I will also say increasing your SS time a bit and tuning the compensation will likely improve the resulting startup.

Thanks,

Sarah