Other Parts Discussed in Thread: BQ25570, BQ25504
Tool/software:
Hi,
I am developing with the BQ25622 and I have a series of questions. In fact I am developing both the hardware solution, but before we implement I am developing a spice simulation of the BQ25622, including its I2C interface. During development of this simulation, I have come to realise that several areas within the datasheet are missing detailed information. I was hoping that you can help.
1. The Dynamic Power Management function primarily controls the buck converters "average"? input current to maintain the 2 setpoints of VINDPM & IINDPM. Firstly how is this input current measured and how often is it both measured and adjusted? Furthermore how often can these registers be updated by I2C and how quickly will the system act on any changes to these registers. What is the maximum update rate? I would like to put the BQ into a closed loop with a uController. these discrete time delay 'sample' characteristics are critical to my design.
2. Related but also distinct; In section 8.3.4.2 which discusses DPM, the second paragraph reads 'When the charge current is reduced to zero', however the charge current can not be programmed to zero, instead the minimum input current can be no less than 100mA. (8.6.2.3 Range: 100mA-3200mA (5h-A0h). Therefore can you clarify if the input current takes a further step towards zero after it reaches 100mA? If so when does this occur. This is very important and it potentially prevents the DPM from pulling the VBUS below its minimum thresholds of 3.7V - POORSRC detection threshold and / or SLEEPZ threshold from VBUS-BVAT. In either case does this last step really occur, i.e. input current reduced to zero. Or does this only happen indirectly when these voltage thresholds are triggered.
3. If VBUS falls below POORSRC threshold this re-triggers an adapter reattach processes, where POORSRC qualification is carried out. From POR or through this mid-charge process how long is the 10mA current source applied for before a 'GOOD/POOR SRC' decision made. Furthermore if qualification fails how often does the BQ enter re-qualification? In other datasheets from other BQ 25X devices I have read every 2mins. However on your forum I have read every 2 seconds, with a permanent fail state after 7 attempts. In the datasheet for the BQ25622 it is not mentioned at all. This is critical information for my design, As I am designing an energy harvester and the VBUS is both intermittent highly variable and unpredictable.
4. Does the device go through POR > POORSRC qualification even when it could operate in supplemental mode. The section 8.3.10.2.6 - Sleep and Poor Source Comparators, is a little confusing:
' it is a new adapter attach, and poor source qualification will be run in addition to D+/D- detection if enabled. VBUS_STAT and the PG pin state will be determined by the adapter attach sequence as outlined in Section 8.3.3.'
The adapter attach process takes place before Section 8.3.3.
The first question is does the device do POR whenever VBUS rises regardless of the state of running in BAT only mode? If I read correctly the POR only occurs if no battery is present i.e. VBUS collapses whilst VBAT is below 2.4V (VBAT_UVLOZ).
Secondly, if the system drops into supplemental mode, according to section 8.3.2 the REGN would be disabled, therefore if VBUS falls below POORSRC threshold 3.7V, would this trigger entry into supplemental mode and would we therefore incur the 220mS delay as any attempt is made to re-enable REGN according to section 8.3.3.1?
I have further questions, but for now, I would be very pleased if you could clarify the above and hopefully after we open a dialogue, I can get into more details.
All the very best
Aidan Walton
