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TPS25981: Design Review for Custom Board || TPS259813A

Part Number: TPS25981

Tool/software:

Dear Team,

Kindly review the below schematics and pcb layout and let me know your feedback.

Schematics Snippet:

Question) Is there a requirement of Gate resistor when using multiple mosfets in parallel?

Layout Snippets: Top View

      

Bottom View

      

Designed on 4L Board with [L1(PWR+GND+SIG) / L2(GND) / L3(PWR+GND+SIG) / L4(PWR+GND+SIG)] Stackup

Power Characteristics: 12V @ 8A(max)

Kindly provide your feedback at the earliest.

Thanks and Regards,

Shashank

Electronics Engineer

  • Hi Shashank,

    I am stuck in lab with some testing. Please expect my reply by end of this week.

    Best Regards,
    Arush

  • Hi Shashank,

    • Why are you using Q2? Is it for Reverse Current Blocking (RCB)?
    • Your falling threshold of OVLO is very close to nominal voltage. It is better to push it little higher. 
    • Your ILIM (8A) is equal to your max current. If you want to operate at max current, keep ILIM little higher (at least by 10%)
    • This will work without gate resistance also since gate of eFuse FET also ramps up slowly (dvdt controlled mechanism) in usual scenarios. It is still recommended to keep gate resistance as in some protection mechanism, gate can be ramped at faster slew rate. 
    • Layout looks fine (from the images you have shared)

    Best Regards,
    Arush

  • Hi Arush, 

    1) Yes, Q2 & Q3 is being used for reverse current blocking. In order to improve power dissipation of the mosfets, 2 of them are being used. 

    3) Peak operating is 6A. Hence 8A is chosen as a limit.

    4) Should I add gate resistors for both the MOSFETs Q2, Q3?

    Regards,

  • 3) Peak operating is 6A. Hence 8A is chosen as a limit

    Then 8A limit is good.

    4) Should I add gate resistors for both the MOSFETs Q2, Q3?

    In general adding gate resistance is better choice. 

    Best Regards,
    Arush