Tool/software:
I'm designing a system around TPS22975 with a 1S1P (3.7V) input.
My downstream load capacitance is around 200uF though this is distributed behind 2 regulators.
I'm concerned that there is no SOA information about the internal transistor or information about maximum rise time dependent on load capacitance as these influence stress on the switching device.
I'd like to configure the device for a 10-90% ~20ms rise time, which for 3.7V input I land on about 16nF.
How can I determine if the stress for this rise time duration is acceptable? How is the maximum rise time determined?