This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS22975: SOA and Maximum Rise Time (Minimum Slew Rate)

Part Number: TPS22975

Tool/software:

I'm designing a system around TPS22975 with a 1S1P (3.7V) input.

My downstream load capacitance is around 200uF though this is distributed behind 2 regulators.

I'm concerned that there is no SOA information about the internal transistor or information about maximum rise time dependent on load capacitance as these influence stress on the switching device.

I'd like to configure the device for a 10-90% ~20ms rise time, which for 3.7V input I land on about 16nF.

How can I determine if the stress for this rise time duration is acceptable? How is the maximum rise time determined?

  • Hi Anatoly, 

    Thanks for reaching out on E2E!

    We don't provide SOA information for our load switches, due to the controlled slew rate that is achievable using our soft-start functionality. The biggest concern that can arise with capacitive loads is inrush current. If your inrush current is less than device operating current, device will work fine.

    I see you are configuring 20mS rise time. Any reason for that? With 10 mSec rise time, you can get ~74mA inrush current considering 200uF COUT.

    There is no maximum value for CT cap. 

    Thanks

    Amrit 

  • Hi Amrit - an old revision had a switching regulator with a nominal SS time of 20ms which I'm trying to replicate.

    With the new TPS22975 I'm still hitting an overcurrent limit at startup with our battery on some startups. I agree with your math that we should see <100mA inrush current, it's possible we are having a different issue with downstream microcontrollers or other digital loads drawing high current during startup which was somehow masked by the previous design.