Tool/software:
Hi team,
Customer design is shown as below. test point is at POR_B ( red circle). During VDD power up, RESET will have a glitch. Yellow waveform is 3.3V VDD. Blue waveform is the waveform on POR_B ( RESET pin). I was wondering why there is a glitch and how to eliminate it. Thanks!
Rayna
Hi Rayna, Thanks for your question!
Can you please confirm if they have FB15 on their board? It seems like there is an inductor on VDD pin. I want to check what is the purpose of it. That is not needed for TPS3820.
If you check the timing diagram for power up, VDD passes threshold Vit, and then RESET become high after td delay. For TPS3820, td delay is defines as 25 ms typ. It looks like this is expected behavior
If you look at the datasheet.,Vpor (power on reset) is defined as 0.4V; this mean the minimum power required to the output to assert is 0.4V. And that's why the RESET signal become low. It stays low almost 25 ms and then de-asserts( become high) again.
But I can tell there is some delay in WDOG_B signal. Please look at the reset is already slowly increasing while VDD=0V. Since they have 1.0 uF cap and 1Mohm, this create a slow transaction on WDOG_B. They should remove 1.0uF capacitor and change it a smaller one.
Sila Atalar
