LM5123-Q1: About the burn near pin 7 (HB terminal)

Hello Katsuki,

Most likely one of the Absolute Maximum Ratings has been violated (see chapter 7.1 of the datasheet).

Please note that the pin where you can see the damage need not be the one that has seen the overstress.
It is normal that the damage which appears as a consequence of an over- or undervoltage stress will happen at some completely different pin.
Any violation of the Absolute Maximum Ratings, even if it only happens for a short Periode of time kann degrade of even damage the part.

If you want to concentrate on the HB pin first, the typical scenario which causes a violation of the voltage ratings is a big ringing, especially undershoots of the switch node.
In that case, the capacitor between HB and SW will get charged to a voltage which is higher than the allowed maximum, which will cause overstress on the HB pin.

You may try to use gate resistors of up to 5 Ohms (please make sure that both resistors will always have the same value).
Or you can try different FETs which are switching slower to minimize the ringing on the switch node.

Best regards
Harry

Hello Katsuki,

Higher gate resistors will make the transitions of the FETs more flat.
The dead-time of the LM5123 is only 20 ns.
The device is using an adaptive dead-time control (break before make concept), but it can only see the signals on its own pins and not the signals behind the gate resistor at the gates of the FETs.
When the gate resistors are too big, it may happen that there is a cross-conduction where one FET already turns on while the other one has not yet fully turned off.

You can try using a snubber in addition to reduce the ringing of the switch node.
Or - as mentioned before - different FETs which are switching slower.

Best regards
Harry

Hello Katsuki,

As you can see from the datasheet, there is not much margin for the undershoot of the switch node and the HB voltage.

I am not certain if the word "synchronous" is used with two different meanings here.

Connecting the sync pin and the TRK pin is o.k. So both parts will run synchronously with the same frequency.

An Asynchronous controller with a diode instead of the high-side FET is not recommended for a higher power application like an audio amplifier
and would destroy all the power savings that you gain with the class-H concept.

Please have a look at our class-H reference design, based on the LM5123:
https://www.ti.com/tool/TIDA-020033 

All information in this correspondence and in any related correspondence is provided “AS IS” and “with all faults” and is subject to TI’s Important Notice: http://www.ti.com/corp/docs/legal/important-notice.shtml 

Best regards
Harry

Hello Katsuki,

I never stated that the HB pin is the one that has suffered from overstress.

Please let me repeat that the pin where you can see the damage need not be the one that has seen the overstress.
It is normal that the damage which appears as a consequence of an over- or undervoltage stress will happen at some completely different pin.

So, please double-check all other pins as well.

As far as I am aware, we do not have any asynchronous controller with Track pin.
To connect an external feedback divider to the control-signal of the audio amplifier, you will need to invert the direction of that signal.

Best regards
Harry.

Hello Katsuki,

I have never heard of such a case.

It would need to be a very bad (or maybe broken) probe with a huge capacitance.

One of these reasons seems to be more likely to cause a damage of the controller:
- The HB pin was probed with a direct 50 Ohm input of the oscilloscope
- The HB pin got shorted to the adjacent BIAS pin (even if it was only for a very short period of time)
- Mechanical force on the package of the controller caused some effect due to issues with the solder joints (e.g. underneath the IC)

Best regards
Harry.

Hello Katsuki,

The negative voltage on the HB pin BEFORE the first switching of the FETs is normal.
The HB capacitor will only be charged (with a positive voltage) when the low-side FET is turns on for the first time.

Elder devices often required an external diode and customers ran into issues because some wrong diode was chosen.
So, we decided to integrate it into the controller to make sure that it will switch fast enough and has very low leakage.

The voltages (VCC and HB) in your screenshot are vey low. Basically too low for a proper operation.
VCC should usually be regulated (down) to 5V.
When the BIAS voltage is bigger than 3.8V, the controller will start working.
But it can not generate 5V on the VCC pin and the HB voltage will be even lower (3.75V in your measurement).

So I would believe that in your setup the BIAS voltage is just around 4.2V.

With such low voltages it is not guaranteed that the FETs are switching properly.
Also, the timing of the FETs can be different than expected and you may encounter false turn on / turn off events going on.
Worst case this may even lead to cross-conduction between the two FETs.

Therefore, please increase the BIAS voltage in your system.
Either make sure that the input voltage will not fall below 5.5V

Or connect the BIAS pin to VOUT instead of VIN.
For startup, VIN will go across the body diode of the high-side FET to VOUT and also to BIAS, so it has to be around 4.5V .. 5V to allow for the controller to start up.
But when the input voltage drops afterwards, the controller will be supplied by the self-boosted output voltage.

This discussion just reminds me of another problem which can occur with a lab setup and which might cause your original issue:
If the lab supply for VIN is running into a current limit it may happen that the boost converter cannot deliver the required energy to the output.
It will also not go into any protective mode as there will never be an overcurrent happening.

This constellation can also damage a converter stage.

So, please make sure that the lab supply will always deliver the required peak inductor current plus same margin.

Best regards
Harry

Hello Katsuki,

> I believe the voltage between HB and SW depends on VCC and the Vf of the internal diode,
This is correct.

> could you tell me how much it varies at a constant temperature (for example, Ta = 25°C)?
1) When the BIAS voltage is high enough, so that the VCC regulator is enabled, the VCC voltage falls between min=4.75V, typ=5V, max=5.25V

2) When BIAS is less than the 5-V VCC regulation target (VVCC-REG), the VCC output tracks the BIAS pin voltage with a small dropout voltage
which is caused by 1.7-Ω resistance of the VCC regulator.
For the Minimum supply voltage VBIAS=3.8V and the maximum load current on the VCC pin IVCC=100mA The minimum VCC voltage is specified as 3.45V.

The VCC voltage will then go across the internal diode, with a HB diode resistance of typically 1.2Ω

Typical values correspond to TJ = 25°C.
Minimum and maximum limits apply over TJ = –40°C to 125°C, unless otherwise stated.

> could you tell me how much the voltage between HB and SW varies with temperature?
- While the regulator is active, VCC varies across temperature from min=4.75V to max=5.25V
- For the HB diode resistance, the datasheet only mentions a typical value of 1.2Ω. So, I would consider about 25% tolerance to the diode resistance.

> If you have any measurement data, please send it to me.
I am sorry, but for parameters which are not listed in the datasheet, we do not capture any data during ATE tests.
If I did take measurements on a single board/device, it would not be representative at all, so I will not spend any time on that.

Best regards,
Harry

Hello Katsuki,

The only realistic countermeasure is to keep the undershoots on the switchnode as small as possible.

Any pre-charged voltage of the HB capacitor will be clipped by an internal diode
Anyway, it is normal and will not harm the device.

All information in this correspondence and in any related correspondence is provided “AS IS” and “with all faults” and is subject to TI’s Important Notice: www.ti.com/.../important-notice.shtml

Best regards
Harry

Hello Katsuki,

The capacitance of the capacitor between SW and HB must not be changed.
Please make sure, that you are using low ESL, low ESR type capacitors.

The best resistance for the gate resistors needs to be determined by experiments and measurements on the physical PCB in the lab.
You can also place a snubber in parallel to the FET.

Most importantly, a good layout with very small parasitics in the power path (especially from the low side FET to PGND) and the gate loops is mandatory.

Again:
The only countermeasure is to keep the undershoots on the switchnode as small as possible.
Everything else (VCC voltage, diode drop) is fixed within the controller.

To be honest, you are the only customer who is so much worried about the HB voltage.
A steady level within the specification is fine and short spikes due to noise are tolerable.

Best regards
Harry