Tool/software:
I'd like some help understanding the effect of a too-small RLIM resistor on the COM-VEE regulation and how to avoid this.
My goal is to choose RLIM such that a variable load can be connected across VDD-COM which may draw anywhere from 5mA to 50mA @ 15V during operation (while using VDD-VEE to supply a gate driver).
Using the design calculator spreadsheet, I can find the resistance that will support the maximum power requirement, but I don't know if this will be a problem during lower power operation. The datasheet mentions potential oscillation if the RLIM resistance is too small. Is there a way to determine what is "too small," and how detrimental is that state of oscillation?
Would you also clear up the following? The datasheet says that the charging and discharging FET-resistor pairs are both controlled based on the FBVEE pin voltage and the same 20 mV of hysteresis. However, Figures 11-2 and 11-3 suggest that the hysteresis for the discharge side is smaller (1.25 mV). Which is correct? It seems this would affect the ability of the circuit to enter a state in which neither resistor is active.
Thanks in advance!
