Full Bridge with SR and side current mode control (no ZVT)

Paolo,

I am sorry that you consider the documentation for the UCC28950 a "mess". The UCC28950 is a very complex part, it provides the design engineer many features to fine tune their design to achieve a very high efficiency power supply. Because of this the documentation is also complex and does require some serious study.

Regarding the UCC28250, you do not have to use this part on the secondary side, as you suggest above. In fact figure 1 in the data sheet shows the UCC28250 used on the primary side. Also there is an evalution module available that demonstrates the UCC28250 on the primary side, UCC282850EVM-501 (http://www.ti.com/tool/ucc28250evm-501).

Also if you study the data sheet for the UCC28250, on page 18 you will find the equation for setting the current sense resistor when used in current mode control. This equation shows using a current sense transformer with turns ratio 1:n, peak ramp voltage is 3V.

I hope some of my inputs here will help you progress your design.

Regards,

Richard.

Hello Richard!

Thank you a lot for your answer.

However, my main concerns are not about the configuration of the UCC28250 current sense.

My main concerns are about how to design the compensation network on the primary side...

On the documentation I've seen that the compensation network is always on the secondary side...

I would like to know how to make it on the primary, in order to avoid the use of very low precision optocouplers (I have to close the loop on 500V output voltage!)...

I sense the voltage with a HCPL7800 (Vout=200mV differential, then I have an Opamp to increase this voltage to the desired value) and I would like to use this output voltage (2.5V typ) as E/A input to achieve peak current mode control.

Could you help me?

Thank you in advance for your help!

PR

Paolo,

I am not familiarwith the HCPL7800, but I see you have a voltage level proportional to the output. This level is 2.5V when the output is in regulation. This voltage can be connected through a resistor to pin 9 of the UCC28250PW. Pin 8 will be your reference, connect to a 2.5V reference, either your own generated reference or a portion of the reference from pin 7 of the UCC28250PW. The compensation network would then connect between pin 10 and pin 9. This would be similar to the set up in figure 2 of the data sheet, but R12/C12 node would connect to the output of your isolation feedback circuit, R13 would be open circuit.

Hope this is clear.

Richard.

To be completely honest, not very much...

My response above describes how to connect your HCPL7800 based circuit output to the UCC28250 with the compensation network on the primary side.

What is it you want? is it that you cannot follow my description?

Richard.

Your description is clear...
I still have some doubt about the following points:

1. DS tell me that in primary side configuration pins 9-10 must be shortened together, you are saying me to put compensation there...  Who is right?

2. Which kind of compensation is necessary to achieve current mode control?  Type 2 or Type 3?  And which is the comparator ramp amplitude, supposing to put 2.5V on pin 9...

Thank you a lot for your help!

PR

Let me respond to your questions.

1. The DS mentions shorting pins 9 and 10 when doing primary side control. This is true when using an external error amplifier, if you look at figure 1 the external error amplifier is the TL431 or D3. Shorting pins 9 and 10 just configures the UCCC28250 internal error amp as a voltage follower. However in your application we are going to use the internal error amplifier and so that is what I describe. Both are right....

2. Usually for current mode control type 2 compensation is sufficient. but since the components used are small I would recommend at least having PCB place holders for type 3, just in case. The ramp amplitude will be between 0.3V and 3V. This will depend on what the duty cycle and output load demand will be when in steady state regulation. it will be some where between 0.3 and 3V. At light load it will be close to 0.3V and full load it will be close to 3V.

Richard.

So, if I understand well, I have to design the compensation netowrk for the worst DC gain possible, so, since it depends from Vout/Vramp, for Vramp=0.3V.

Is it correct?

Are you confusing the gain of voltage mode control, which is Vin/Vramp, with current mode mode control?

The gain for the PWM stage in current mode control is very different and is related to to the slope of the current during the ON time and the slope of any additional ramp added for slope compensation.

CMC PWM gain = 1/((mc + mn)*Ts), mc is the slope of the ramp of any slope compensation that may be added (V/s), mn is the slope of the current during the ON time (V/s), Ts is the switching period (s).

Regards,

Richard.