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LM7310: Priority Muxing not working as expected and design review needed.

Praful Dhanawade
Prodigy 30 points
Part Number: LM7310

Tool/software:

Hello everyone,

We are testing an ORing circuit using the LM73100 ideal diode controller and are encountering an unexpected voltage dip of approximately 2-3V for 6ms. I would appreciate any insights on this issue.

Circuit Setup:

    • Load Current (Considering RIstart as 6ohm): 2A ( Maximum load of 5A and continuous load of 3A)
    • Input Voltages: Primary Power Supply = 12V, Secondary Power Supply = 12V
    • Output Capacitance: 470µF
    • Cdvdt: 1.8nF
    • DSO Probe Color Mapping:
      • Green: 12V_ORing (output)
      • Blue: Secondary Power Supply
      • Yellow: Primary Power Supply

Test Scenarios & Results:

Test 1 (Ideal Condition - DSO Image 1: oring_01.png)
  • Initial State: First Primary Power Supply is turned ON, then Secondary Power Supply is turned ON
  • Transition Trigger: Primary Power Supply turned OFF
  • Observation: Power switching works as expected although there is voltage dip of approximately 2-3V
Test 2 (Failure Case - DSO Image 2: oring_02.png)
  • Initial State: First Secondary Power Supply is turned ON, then Primary Power Supply is turned ON
  • Transition Trigger: Primary Power Supply turned OFF
  • Observation: The ORing output fails and the output of ORing is turned off completely
Test 3 (Simultaneous Startup - DSO Image 3: oring_03.png)
  • Initial State: Both supplies turned ON at the same time
  • Observation: The ORing output gradually ramps up, showing how the circuit behaves during a cold start when both supplies are activated simultaneously.
  • A wider view of Test 3, showing the ORing behavior over a longer timespan.

Issue:

According to calculations, the slew rate should be sufficient, but during actual testing, we see an approximate 2-3V voltage droop in certain cases. This could potentially impact system stability at higher loads (target 5A).

Request for Help:

  • Is this voltage dip expected given the component values?
  • Could there be an issue with Cdvdt selection or output capacitance?
  • Any suggestions to mitigate the voltage dip and ensure a smooth transition?
  • Why does the ORing output fail in Test 2?
  • Is there any internal fault latch that is being triggered which leads to failure in Test 2?

Attached are DSO images and data files for reference. Looking forward to your opinions!

Thanks in advance! and kindly let me know if any additional information is needed from my end.

  • 0
    TI__Mastermind 38885 points

    Hi Praful,

    Can you zip all the pictures and add that zip here. For some reason, these images are not loading here. Kindly use names mentioned above and I will check the description from above. Also it looks like you uploaded a xlsx file which is also not loading so include that also in the zip file.

    Best Regards,
    Arush

  • 0 in reply to Arush Gupta
    Prodigy 30 points

    Hi Arush, thanks for reaching out. I have attached the necessary along with this message. kindly not to consider the colors in DSO images according to how I have mentioned in my question earlier.

    DSO Exports.zip

  • 0 in reply to Praful Dhanawade
    TI__Mastermind 38885 points

    Hi Praful,

    Thank you for sharing the files. 

    Praful Dhanawade said:
    Test 1 (Ideal Condition - DSO Image 1: oring_01.png)
    • Initial State: First Primary Power Supply is turned ON, then Secondary Power Supply is turned ON
    • Transition Trigger: Primary Power Supply turned OFF
    • Observation: Power switching works as expected although there is voltage dip of approximately 2-3V

    It looks like the out is still supplied by the VIN1 for some time which is causing the drop and after the switch to VIN2, the output caps start charging. 

    What is the cause of this spike in VIN1?

    Praful Dhanawade said:
    Test 2 (Failure Case - DSO Image 2: oring_02.png)
    • Initial State: First Secondary Power Supply is turned ON, then Primary Power Supply is turned ON
    • Transition Trigger: Primary Power Supply turned OFF
    • Observation: The ORing output fails and the output of ORing is turned off completely

    It looks like the transition never happened here. Can you share your schematic. How are you implementing the ORing?

    In first test also, transition should have happened lot earlier. 

    Praful Dhanawade said:
    Test 3 (Simultaneous Startup - DSO Image 3: oring_03.png)
    • Initial State: Both supplies turned ON at the same time
    • Observation: The ORing output gradually ramps up, showing how the circuit behaves during a cold start when both supplies are activated simultaneously.
    • A wider view of Test 3, showing the ORing behavior over a longer timespan.

    This looks fine. Just want to confirm, are you doing muxing or oring. This looks like Vout is equal to VIN1 even though it is lesser. 

    Praful Dhanawade said:
    According to calculations, the slew rate should be sufficient, but during actual testing, we see an approximate 2-3V voltage droop in certain cases. This could potentially impact system stability at higher loads (target 5A).

    This Oring is based on RCB and not on startup of device. So it shouldn't depend on startup slew rate. 

    Praful Dhanawade said:
    • Is this voltage dip expected given the component values?
    • Could there be an issue with Cdvdt selection or output capacitance?
    • Any suggestions to mitigate the voltage dip and ensure a smooth transition?
    • Why does the ORing output fail in Test 2?
    • Is there any internal fault latch that is being triggered which leads to failure in Test 2?

    I can only tell after seeing how you have implemented the Oring/muxing.

    Best Regards,
    Arush

  • 0 in reply to Arush Gupta
    Prodigy 30 points

    Hi Arush,

    I am using the LM7310 in a Priority Muxing arrangement. I have attached the Schematic along with this message for your reference. 

    Arush Gupta said:
    It looks like the out is still supplied by the VIN1 for some time which is causing the drop and after the switch to VIN2, the output caps start charging. 

    Kindly help me understand why you think the Vout is being powered by Vin1 as the Vin1 input has been cutoff. During the switch over the Vout is powered by the Cout.

    Arush Gupta said:

    What is the cause of this spike in VIN1?

    I am unaware what would cause the voltage spike.

     lm7310 Priority Muxing.zip

  • 0 in reply to Praful Dhanawade
    TI__Mastermind 38885 points

    Hi Praful,

    Apologies for delayed response. Is this still an issue?

    Your primary supply (yellow channel SMPS) is somehow not turning off when dropping below 11V (uvlo threshold set). I suspect that either probing is mixed between SMPS and Aux power supply and yellow is Aux channel as it looks like it is turning off at near 8.7V (UVLO threshold for AUX channel) or resistor got mixed or some other voltage rail is keeping EN high. Checking EN and OVLO voltage for both channels will help you in debugging.

    Best regards,
    Arush