TPSM843A26E: TPSM843A26RDGR-ET

Kavin Ravi

Part Number: TPSM843A26E
Other Parts Discussed in Thread: TPSM843A26,

Tool/software:

Hi,

We are using the TPSM843A26RDGR-ET in one of our products and have recently completed the schematic design. Before proceeding with the PCB layout, we would like to run a simulation to validate the design. However, we could not find the relevant library in PSpice for TI.

Could you assist us by verifying our schematic and providing a simulation report? Additionally, to estimate the values of RENT and RENB, could you provide the pull-up current source (IP) and pull-up hysteresis current (Ih) values?

Thank you.

Kavin

6 months ago

0 David_Daniels 6 months ago

TI__Mastermind 23955 points

Hello Kavin,

TPSM843A26 is the function same as TPSM843A26E, the E version has additional qualifications.

The pspice model from the TPSM843A26 product folder on ti.com. https://www.ti.com/lit/zip/slum897 can be used to simulate.

Webench can be used to calculate the enable pin resistors in the left panel or equations in ds. The Ip is 1.5uA and Ih is 9.9uA.

Webench is available at the bottom of the TPSM843A26 product folder TPSM843A26 data sheet, product information and support | TI.com

EC table on page 5 has the Ip and Ih.

https://www.ti.com/lit/ds/symlink/tpsm843a26e.pdf#page=5

I can review the schematic.

Regards.

David

0 Kavin Ravi 6 months ago in reply to David_Daniels

Prodigy 110 points

Hi David,

Thank you for your prompt response. I have created a schematic using the values from Webench. I would appreciate it if you could review it.

Please note that the 1V_EN (Enable) signal is a 1.8V supply provided by an LDO from the PMIC.

0 David_Daniels 6 months ago in reply to Kavin Ravi

TI__Mastermind 23955 points

Kavin,

The design looks good. However, if your output load current step is large, consider using more output capacitance.

Use the pcb layout in figure 8-17 https://www.ti.com/lit/ds/symlink/tpsm843a26e.pdf#page=31 for guidance.

The TPSM843A26EVM on page TPSM843A26EVM Evaluation board | TI.com is a 12V to 1V design and there are performance waveforms in the user guide.

Best Regards,

David

0 Kavin Ravi 6 months ago in reply to David_Daniels

Prodigy 110 points

Hi David,

Thank you for your feedback. We expect a maximum of 10A from the buck converter for the 1V VDD of the processor. I have included 0.1µF, 1µF, and 10µF capacitors on both of the VOUT. Is this sufficient, or would you recommend adding an extra 100µF capacitor on both sides of the VOUT?

Additionally, is there a way to determine how long it takes for the buck converter to deliver 1V after receiving the enable signal, in milliseconds?

Also, can I just connect the GND to AGND while designing the PCB?

Regards,

Kavin

0 David_Daniels 6 months ago in reply to Kavin Ravi

TI__Mastermind 23955 points

On the left panel in webench, there is a selection for Custom output specs. The needed information is voltage transient and output current step.

If the step is 0A to 10A, use 10A. If the transient change can be 5% then the output capacitance should be around 600uF of output capacitance.

Since the capacitance of ceramic capacitor vary with dc voltage,

the Ceramic capacitor should be derated for the dc bias, below is an example graph of capacitance change vs dc bias

See figure 8-11 on page 29 https://www.ti.com/lit/ds/symlink/tpsm843a26.pdf#page=29 show the startup timing of vout with enable.

The ramp time of Vout is a soft start which can be 1ms, 2ms, 4ms or 8ms depending of the msel resistor value. see table 7-5 on page 18 datasheet.

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TPSM843A26E: TPSM843A26RDGR-ET