Tool/software:
Dear TI Team,
I am designing a PFC system for an aircraft application with an input operating range of 90Vrms to 134Vrms and a frequency range of 360Hz to 800Hz.
The peak load for the design is 300W, while the standby load ranges from 20W to 25W.
I have followed the datasheet for design calculations, where the voltage error amplifier and feedforward voltage are directly proportional to current harmonics.
I need to limit the third-order harmonics to within 3%, and I have designed the feedforward and voltage error amplifier accordingly for peak load conditions. However, I also need to limit the third-order harmonics during standby load operation.
Does the current error amplifier play any role in reducing harmonics? How can I achieve the required harmonics percentage in both full-load and standby-load operations?
Additionally, if there are any documents related to current harmonics reduction using this IC, please let me know.
Regards,
Aravind S.
