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LM5176: Urgent - CS, CSG current limit tweaks

C Long
Prodigy 100 points
Part Number: LM5176

Tool/software:

Hi

I have a design that's worked well for several years. Recently I had a need to allow higher current spike (uSec range) pass, ie not cause an overcurrent event. We quickly changed 6mOhm resistor between Cs and Csg to 3mOhm as the most readily available alternative. With 12V and 12V out I'm not sure this is stable anymore and the simulation shows huge ripple. Do I need to change some other component to compensate? Cslope perhaps?

This is a line down situation!

webench.ti.com/.../SDP.cgi

  • 0
    TI__Guru 58641 points

    Hi,

    when changing the Sense Resistor you should also check and adjust the slope compensation

    -see: SNVSAI1 Data sheet | TI.com

    Also checking the compensation would be good as the power stage will have higher output current which can impact the loop stability.

    Furthermore the saturation current of the inductor needs to be checked. With the higher current the inductor can run into saturation which can results in an unstable output voltage or even an damage of the power stage.

    Best regards,

     Stefan

  • 0 in reply to Stefan Schauer
    Prodigy 100 points

    Hi Stefan,

    We increased the output capacitance resulting in a lower ESR. This reduced the output ripple and the inductor current to safe figures. We didn't change anything else and this seems to work well. Does that makes sense to you?

    FYI - I have found that once we have run 20 or 30 simulations on a model it no longer allows us to run more. I've rebuilt the model starting from scratch and the same thing happened again after 28 simulations. Is there a limitation with Webench Power designer in this regard? This makes simulating things painful !

  • 0 in reply to C Long
    TI__Guru 58641 points

    Hi,

    as the current spike are only in the usec range this could be buffered by the output caps - so makes sense.

    If changing the output caps you should check your loop stability (Gain and Phase margin) and adjust if required the components on COMP pin.

    I do not know of any limitations for the Webench. Best would be to check with the Webench team.

    I can either forward this thread to the webench team to check but then you need to enter a new thread if you have a follow on question here. 

    Or you enter a new thread directly assigned to the webench  team for checking the simulation question.

    If I should forward just let me know - otherwise I assume you will enter a new thread for webench.

    Best regards,

     Stefan

  • 0 in reply to Stefan Schauer
    Prodigy 100 points

    Hi Stefan,

    1 related question - when we see 16A spikes for ~400uS it causes problems for the upstream PSU feeding the LM5176. Essentially it has a lower current limit. Do you have any recommendations on how to 'filter' these out as part of this design?

  • 0 in reply to C Long
    TI__Guru 58641 points

    Hi,

    so you would need a current limit on the input.

    Depending on the length and height of the current spikes an increased input cap might help but might be then to large.

    Another option would be to use the average current limit on the input side to limit the current into the power stage but that might require an redesign.

    In this case you also need to accept that the output voltage will drop in the case of the current limit triggering.

    Best regards,

     Stefan