TPS631010: parallel with an LDO

Hi  Lgnacio,

I am afraid it is not a good idea because there will be a time delay between EN pulled high and  first switching cycle. This feature will cause a voltage drop at output not.

For most DCDC converter and LDO, this delay should always have.

Regards

Tao

Hello Tao

Okay, and why if I use individual pins and I apply a delay in order to avoid a dropdown? Can the regulators operate in parallel for a brief time?

Cheers

Ignacio

Hi,

Tao will reply tomorrow. Thanks.

Hi  Ignacio,

Individual pin may work, but it is difficult to apply a precise delay, right?  What is the purpose to have them in parallel? 

Regards

Tao

Hello Tao

The purpose of this design is to have the LDO regulator to power the board when the processor is idling or in low power modes

in which the efficiency difference isn't that important. However in higher power modes, the efficiency really matters, so is better to have a switchmode regulator there specially if we count with the efficiency figures of the TPS631010

Also in lower power modes the board runs ADC measurements so having the ability to switch between LDO and a DC/DC is a plus

Hi  Ignacio,

Got it. but i think TPS631010's efficiency performance in light load is not bad, since Vin is not a constant and stable one, i think efficiency performance of LDO should be even worse under some Vin, right?

Below is efficiency curve of TPS631010, could you let me know which light load points do you mean, and also what is your target of efficiency?

Regards

Tao

Hey Tao

Effectively, efficiency of TPS631010 ys very good at low output currents, getting near or better thant the LDO efficiency (78% at 4.2V vin)

My problem here is that I couldnt find the TPS631010 quiescent current when switching at PFM mode and with light load (40uA) The figure stated in the datasheet is for no switching condition and Vin of 2.2V. I don't know if the quiescent current is included in the efficiency figure or if it is unknown.

Then, the idea of the LDO is in general to mantain the idling or powered down system as quiet as possible, and a switching regulator is not very quiet as far as I know

cheers

Ignacio

Hi  Igbacio,

Quiescent current is included in efficiency figure. that is sure.

Yes, you are right, switching regulator always can be the noise source and LDO is a quiet. 

Is it possible you can enable TPS631010 before your down system switch to heavy load mode? I mean may be 1ms ahead.

Regards

Tao

Hey Tao

Okay for the quiescent current.

Regarding the delay, its okay too. I can add any delay from the board's microcontroller. I even included circuitry in order to assure that the board's power is never removed by accident.

My main question is if the LDO and the DC/DC converter can operate (at the same output voltage) for some time, and if they can can operate indefinitely with the other regulator powered down and connected in parallel

cheers

Ignacio

Hi, 

Tao will reply after weekend. Thanks.

Hi  Ignacio,

For TPS631010, i would like to say it is ok to work in parallel with LDO.

Regards

Tao

Hello Tao

can you confirm that the TPS631010 can work in parallel to an LDO?

Best

Ignacio