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UCC27282: UCC27282

Yoni Zlotnick
Prodigy 80 points
Part Number: UCC27282

Tool/software:

Hi

I am intending to use the UCC27282 for a full bridge implementation 

The Vin will be 36-60V /400-600W

What is the parameters for choosing the right N-ch MOSFET the the Driver will support ?

  • 0
    TI__Expert 7475 points

    Hi Yoni,

    Our gate drivers can drive almost any FET, so the FET choice is up to your system needs. From a gate driver perspective, you will need to make sure that proper VDD bypass capacitors, bootstrap circuits, gate resistance, and efficient layout is made.

    This app note can help with bootstrap circuitry: https://www.ti.com/lit/an/slua887a/slua887a.pdf

    This app note can help with gate resistance: https://www.ti.com/lit/ab/slla385a/slla385a.pdf

    Layout guidelines can be found in the datasheets of all gate drivers.

    Please let me know if you have more questions.

    Thanks,
    Rubas

  • 0 in reply to Rubas Khalid
    Prodigy 80 points

    Hן Rubas

    The information that you attached were imported but did not answer the question of what are the parameters to match FET to Driver

  • 0 in reply to Yoni Zlotnick
    TI__Expert 7475 points

    Hi Yoni,

    The FET parameters that will matter when selecting a gate driver is as follows:

    Vgs: This is used to determine if the gate driver has a high enough VDD spec to support the FET VGS. For example, if you intend to drive a FET from -5V to 20V (common for SiC/IGBTs), then a driver that has a maximum VDD spec of 20V will not be sufficient as you need a total of 25V to drive that FET.
    Qg: This is used in conjunction with your desired rise/fall time (t) to determine if the gate driver has a high enough peak current to support FET switching speed.

    You can use the above parameters to calculate the equivalent capacitance (Ceq) of the FET and see if the gate driver has high enough peak current (Ipk):
    1. Ceq = (Qg / Vgs)
    2. Ipk = Ceq * (Vgs / t)

    You should also make sure that your selected gate driver can handle the power dissipation using the following system parameters:
    VDD: This is the voltage used to power your gate driver and drive your FETs.
    fsw: This is the switching frequency for your FETs in your system.
    Ta: This is the maximum ambient temperature you expect in your system.
    Tj: This is the maximum junction temperature for the gate driver you selected (found in gate driver datasheet).
    RθJA: This is the junction to ambient thermal resistance for the gate driver you selected (found in gate driver datasheet).

    The above parameters are used to calculate power dissipation, where Tj cannot exceed the gate driver maximum Tj spec:
    1. P = Qg * VDD * fsw
    2. Tj = (P * RθJA) + Ta

    Thanks,
    Rubas